Chetana Harapanahalli — Head of Design

As a layout design engineer Sr I at Synopsys, I work on analog and mixed-signal layout design for various semiconductor nodes, ranging from 3nm to 90nm. I have successfully completed layout design for blocks such as PLL, LDO, SerDes, and more, ensuring compliance with design rules, quality standards, and customer specifications. I have a strong background in electronics and communication engineering, with a BE degree from SKSVMACET. I have developed and honed my skills in semiconductors, electronics, and VLSI, as well as debugging, floorplanning, placement, routing, and verification. I am passionate about learning new technologies and techniques in the field of layout design, and I strive to deliver high-quality and innovative solutions.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and analog layout design.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs 9 mos