Suvendu Saha — Software Engineer

Currently working as an Application engineer where my responsibilities are Qualification of VCS through Onsite testing, Customer engagement and debugging of design failures followed by providing solution/Workarounds till issue gets resolved in Simulator. Previously worked as Principal Product validation Engineer in Cadence Design systems having 9 yrs of experience in Verilog / SystemVerilog and mixed-language where being a first user my job involves writing tests in Systemverilog / UVM to validate features implemented in simulator. Experience in all levels of testing, including Performance, Functional, Integration, System, Regression and User acceptance testing. Works Include : - Implementing Unit and Integration tests in systemverilog to consistently deliver high quality features. - Coordinate continued performance assurance of software applications and automated performance test scripts. - Identified areas of the application to be regression tested. - Verification of SystemVerilog features (functional and performance) implemented in Xcelium through automation (using Python) which includes random test generation covering different constructs and scenarios. - Responsible for giving trainings on SystemVerilog to new joiners.

Stackforce AI infers this person is a highly skilled EDA engineer specializing in verification and validation.

Location: Faridabad, Haryana, India

Experience: 15 yrs 8 mos