Deepank Yadav

Product Engineer

New Delhi, Delhi, India3 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in SystemVerilog and UVM for memory controller verification.
Proven track record in debugging complex verification issues.
Strong experience in developing robust verification checks.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in memory controller technologies.

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Skills

Core Skills

SystemverilogVerification Ip

Other Skills

UVMDFI-DDR5HBM4 Memory ControllerLPDDR6 PHY VIPdebuggingregression stabilizationverification checksSystem on a Chip (SoC)Static Timing AnalysisRTL DesignCircuit DesignVerilogApplication-Specific Integrated Circuits (ASIC)EngineeringProject Management

About

Senior R&D Verification Engineer specializing in next-generation DDR, LPDDR, and HBM memory controller verification. Strong expertise in SystemVerilog and UVM, with proven experience in debugging complex issues, regression stabilization/cleanup, and development of robust verification checks

Experience

3 yrs 11 mos

Total Experience

3 yrs 11 mos

Average Tenure

Current Experience

Synopsys inc

Senior Research And Development Engineer

Jul 2022 – Jun 2026 · 3 yrs 11 mos · Delhi, India

Development & Verification of VIP (Verification IP) components for DFI-DDR5
MRDIMM, HBM4 Memory Controller. Worked on the developing and verification of the LPDDR6 PHY VIP. Identify & resolved complex functional failures in subsystem Verification
IP, directly contributing to enhance design robustness.
Worked on the coverage and multiple checks to sign off the verification

SystemVerilogUVMDFI-DDR5HBM4 Memory ControllerLPDDR6 PHY VIPVerification IP+3