Ajay Yadav — Software Engineer

Enthusiast Engineer with over 3.5 years of experience in memory designing and characterization. Have been in member of team for delivering and developing Memory Compiler with some of technology nodes such as 5nm,7nm,12nm,14nm,22nm,28nm,40nm. ........................................................................... Working in Synopsys (India) Pvt. Ltd. as Sr. R&D Engineer I. MTech from NIT Patna with Microelectronics & VLSI Design. Flexible to work in any environment as required. ........................................................................... Subject Knowledge: CMOS circuit design, Analog circuit design, Digital Electronics, ASIC, Low power VLSI, VLSI Testing and Testability. .......................................................................... HDLs Verilog : [ Data types | Operators | Assignments | Delays | Begin-end | Fork-join | Looping & Branching construct | Task & Function | Complier Directives | File IO Operations | FSM Coding | Scheduling Semantics | Pipelining | Synthesis issues]. ........................................................................ HVLs System Verilog: [ Data types | Task & Function | Interface | Mailbox | OOPs | Constraints & Randomization | Threads | Semaphore | Functional Coverage] ........................................................................ Programming Skills : C,C++, OOPs Concept. ......................................................................... EDA Tool used : Verilog HDL simulation - Vivado, Modelsim, Edaplayground Schematic to Layout - Cadence Virtuoso

Stackforce AI infers this person is a VLSI design engineer with expertise in semiconductor technology.

Location: Patna, Bihar, India

Experience: 3 yrs 11 mos