A

Ashwith Garlapati

Software Engineer

Hyderabad, Telangana, India2 yrs 10 mos experience

Key Highlights

  • Expert in VLSI design and power optimisation.
  • Proficient in multiple programming languages including C and Python.
  • Experienced in using advanced tools like Fusion Compiler and Synopsys Formality.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and ASIC development.

Contact

LinkedIn

Skills

Core Skills

Fusion CompilerLogic SynthesisSynopsys FormalityElectrical Engineering

Other Skills

PNRLECCshTCLField-Programmable Gate Arrays (FPGA)Design OptimizationApplication-Specific Integrated Circuits (ASIC)VHDLVery-Large-Scale Integration (VLSI)C (Programming Language)Python (Programming Language)VerilogSystemVerilogLinuxDigital Electronics

Experience

2 yrs 10 mos
Total Experience
--
Average Tenure
--
Current Experience

Synopsys inc

3 roles

RD Sr Engineer

Promoted

Feb 2025 – Present · 1 yr 4 mos · On-site

Fusion compilerLogic SynthesisPNRLECSynopsys FormalityCsh+13

R&D Engineer

Jul 2023 – Jan 2025 · 1 yr 6 mos · On-site

CshSynopsys Formality

Technical Engineer

Aug 2022 – Jul 2023 · 11 mos · On-site

  • Worked on the VLSI design for PPA optimisations in all stages of physical design, along with the flow migration of the design. Focused on Power Optimisation for the VLSI designs.
LinuxElectrical Engineering

Electronics corporation of india limited (ecil), department of atomic energy, government of india.

Intern

Jun 2021 – Jul 2021 · 1 mo · Hyderabad, Telangana, India

VHDLVerilog

Education

Kalasalingam University

Bachelor of Technology - BTech

Jan 2019 – May 2023

Stackforce found 100+ more professionals with Fusion Compiler & Logic Synthesis

Explore similar profiles based on matching skills and experience

MS

Mahammad Rafi Shaik

ASIC Digital Design Staff Engineer

at Synopsys Inc

Bengaluru, India5 yrs 5 mos exp
VerilogVery-Large-Scale Integration (VLSI)
RP

Ranjeet kumar Parida

Research And Development Engineer

at Synopsys Inc

Bhubaneswar, India3 yrs exp
Physical DesignFusion compiler
AS

ABHISHEK SINGH

Lead Member of Technical Staff

at Siemens EDA (Siemens Digital Industries Software)

Delhi, India5 yrs 8 mos exp
Formal Verification
YG

Yeswanth praveen Guntupalli

Senior Product Validation Engineer - Emulation - Low Power Verification

at Synopsys Inc

India3 yrs exp
Low-power DesignAutomation
AC

Ayan Kumar Chatterjee

Staff Engineer

at Samsung Semiconductor

Baduria, India8 yrs 9 mos exp
Mixed-Signal Integrated CircuitsSerDesAnalog Circuit DesignTesting AutomationProject Management
Akhil George Francis

Akhil George Francis

Senior Application Engineer

at Synopsys Inc

Ernakulam, India3 yrs 5 mos exp
SynthesisOptimization
Suman S

Suman S

Senior Application Engineer

at Synopsys Inc

Bengaluru, India2 yrs 11 mos exp
Digital ImplementationPhysical Design
Sai Pavan Kumar Jagarlapudi

Sai Pavan Kumar Jagarlapudi

ASIC Physical Design, Sr Engineer

at Synopsys Inc

Hyderabad, India1 yr 11 mos exp
Physical DesignStatic Timing Analysis