Sai Pavan Kumar Jagarlapudi

Software Engineer

Hyderabad, Telangana, India1 yr 11 mos experience

Key Highlights

  • Expert in ASIC Physical Design for advanced technology nodes.
  • Proficient in static timing analysis and physical verification.
  • Hands-on experience with leading EDA tools like Synopsys.
Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC Physical Design and Verification.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Place & RouteClock Tree SynthesisPhysical VerificationDesign Rule Checking (DRC)Layout Versus Schematic (LVS)Power AnalysisSynopsys IC CompilerSynopsys PrimetimeRedhawkLogic SynthesisSynopsys FormalityFormal VerificationTCLVerilogASIC

About

ASIC Physical Design Engineer experienced in pnr implementation, STA convergence and PV in leading edge technology nodes (3nm/4nm/8nm/16nm). >> Proficient in areas like floorplanning, placement, CTS, routing and STA. >>Experienced in Physical Verification activities which includes DRC, LVS, Antenna, DFM checks. >> Static IR drop Analysis

Experience

1 yr 11 mos
Total Experience
1 yr 11 mos
Average Tenure
1 yr 11 mos
Current Experience

Synopsys inc

2 roles

ASIC Physical Design, Sr Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Physical DesignPlace & RouteClock Tree SynthesisStatic Timing AnalysisPhysical VerificationDesign Rule Checking (DRC)+16

Physical Design Intern

Jul 2023 – Jul 2024 · 1 yr · Bengaluru, Karnataka, India · On-site

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI Design

Sep 2022 – Jun 2024

Bapatla Engineering College

Bachelor of Technology - BTech — Electronics and communication engineering

Jan 2017 – Jan 2021

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