Shreyam Pandey

Software Engineer

Bengaluru, Karnataka, India2 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in C++ and VHDL for formal verification tools.
Proven track record in developing scalable engineering solutions.
Strong foundation in software development and EDA tools.

Stackforce AI infers this person is a Software Development Engineer specializing in formal verification tools and EDA solutions.

Contact

Skills

Core Skills

C++VhdlJavaJavascript

Other Skills

SystemVerilogC (Programming Language)Google Charts APIObject-Oriented Programming (OOP)Problem SolvingCloud ComputingWeb DevelopmentMySQLPython (Programming Language)MongoDBCascading Style Sheets (CSS)Machine Learning

About

I am a Senior R&D Engineer at Synopsys, contributing to the development of Formality, a leading formal verification tool. My expertise lies in software development with C++, complemented by experience in Python, VHDL, Verilog, and EDA flows. I started my journey at Synopsys as an intern and have since worked on developing new features, fixing critical issues, and improving tool performance. I am keen on furthering my career in software development, with a focus on building scalable and reliable engineering solutions.

Experience

2 yrs 9 mos

Total Experience

2 yrs 9 mos

Average Tenure

2 yrs 9 mos

Current Experience

Synopsys inc

3 roles

Senior Engineer, R&D Engineering

Promoted

Feb 2025 – Present · 1 yr 4 mos · On-site

R & D Engineer

Aug 2023 – Jan 2025 · 1 yr 5 mos · On-site

Technical Engineering Intern

Mar 2023 – Jul 2023 · 4 mos · On-site

VHDLC++

Bmc software

Software Development Intern

Feb 2022 – Jul 2022 · 5 mos · Bengaluru, Karnataka, India

Created an Active Link Visualizer which enhances the readability and reduces the complexity of the log file captured by the product of the company, BMC remedy.

JavaJavaScript