AMBIKA S

Software Engineer

Bengaluru, Karnataka, India10 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

5+ years of experience in FPGA/CPLD RTL design.
Proficient in VHDL, TCL scripting, and MATLAB tools.
Experience in Agile development methodology.

Stackforce AI infers this person is a Hardware Engineer with expertise in FPGA design and embedded systems in the Healthcare sector.

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Skills

Core Skills

FpgaRtl Coding

Other Skills

FPGA firmware designRTL designNIOSII soft processor-based designscustom IP generationdesign verificationElectrical EngineeringMatlabMicrosoft OfficeTestingVerification and Validation (V&V)Agile MethodologiesCPrototypingEclipseSimulink

About

-Overall 5+ years of experience in FPGA/CPLD RTL design. -Adept at specification, architecture, RTL coding, simulation(functional and gate level), synthesis, static-timing analysis and verification (functional and formal). -Proficient in VHDL, TCL scripting, shell scripting with good experience in using Altera Quartus, ModelSim, QuestaSim, Lattice Diamond, MATLAB tools. -Extensive knowledge of FPGA design flows and embedded processors(Nios ll). -Knowledge on end-to-end firmware design process including Requirement and Test plan creation, verification - DOORS, Design reviews – CDR, TDR, EDR -Experience in using Project/ Configuration management tools like Jira, Rally, GIT, ClearCase -Project execution using Agile development methodology -Ability to work with challenging and cutting-edge technologies, good communication and leadership skills, teamplayer

Experience

10 yrs 10 mos

Total Experience

3 yrs 8 mos

Average Tenure

4 yrs 2 mos

Current Experience

Cisco

Hardware Engineer

Apr 2022 – Present · 4 yrs 2 mos · Bengaluru, Karnataka, India

Ge healthcare

3 roles

Senior Software Engineer

Jul 2020 – Jun 2022 · 1 yr 11 mos

Embedded System Engineer

Promoted

May 2018 – Jul 2020 · 2 yrs 2 mos

. FPGA firmware designer for Interventional Positioner System
. Worked on conceptualization of firmware design architecture, involved in Technical Design Reviews with global counterparts, developing proof of concepts and design risk mitigation
. End-to-end firmware development involving RTL design, NIOSII soft processor-based designs, generation of custom IPs and integration, integration of design constraints, synthesis and development of test benches for functional simulation and regression analysis, and design verification(functional and formal)

FPGA firmware designRTL designNIOSII soft processor-based designscustom IP generationdesign verificationFPGA+1

Edison Engineer

Jul 2016 – May 2018 · 1 yr 10 mos

. Part of GE Edison Engineering Leadership Program(EEDP)
. Part of Motion sensor integration project for Ultrasound system
. FPGA designer for control board for CT Power Distribution Unit

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Intern

Jun 2015 – May 2016 · 11 mos · WHITEFIELD, BANGALORE, INDIA

Worked in Discrete Motion And Drives Department on the project " Modeling and Automated testing of Medium Voltage Drives in Hardware-In-Loop Systems(HiLS) ".