Tejasvi P C

Intern

Hyderabad, Telangana, India0 mo experience

Key Highlights

Proficient in RTL coding and Cadence tools.
Hands-on experience in VLSI design and verification.
Strong foundation in digital circuit design.

Stackforce AI infers this person is a VLSI design intern with a focus on semiconductor engineering.

Contact

Skills

Core Skills

Rtl CodingCadence Tools

Other Skills

Field-Programmable Gate Arrays (FPGA)Physical DesignDFTCadence VirtuosoIntel Quartus PrimeXilinx VivadoDigital Circuit DesignDigital IC DesignVerilogStatic Timing AnalysisMicrosoft PowerPointDigital ElectronicsGitHubGitMachine Learning Algorithms

About

An eclectic Electronics and Telecommunication undergraduate with an M.Tech specialization in VLSI, eager to use both technical and non-technical expertise to achieve objectives. Passionate about contributing, learning, and making a positive impact in dynamic environments. Adept at setting visions and goals, which facilitate informed and automated decision-making.

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Microchip technology inc.

Intern

Feb 2026 – Present · 4 mos · Hyderabad

Field-Programmable Gate Arrays (FPGA)

Chips to startup (c2s)

VLSI Intern

Oct 2025 – Jan 2026 · 3 mos · B.M.S. College of Engineering, Bull Temple Road, Bengaluru - 560019, Karnataka, India · On-site

Worked on a VLSI internship covering the complete RTL-to-GDSII design flow using Cadence tools (xilium, Genus,Modus, Innovus, Tempus, LEC). Designed and verified digital circuits. Gained hands-on experience in synthesis, physical design, STA, formal verification, and DRC/LVS for tape-out-ready designs.

Cadence ToolsRTL Coding