Shouvik Mukhopadhyay

Software Engineer

Bangalore, Karnataka, India5 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expert in RTL and Functional Verification
  • Strong background in GPU and Memory Subsystem verification
  • Proficient in SystemVerilog and UVM methodologies
Stackforce AI infers this person is a Design Verification Engineer specializing in GPU and SoC verification.

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Skills

Core Skills

Rtl VerificationFunctional Verification

Other Skills

Test PlanningFormal VerificationSystem on a Chip (SoC)DebuggingSystemVerilogApplication-Specific Integrated Circuits (ASIC)CC++VerilogPerlPythonUniversal Verification Methodology (UVM)LinuxEmbedded CKeil

About

My current role is Senior Design Verification Engineer in Nvidia Graphics Pvt. Ltd. I have work experiences in Unit and Subsystem level Design Verification in Nvidia Data centre and Automotive based projects and fullchip level verification in GPU project. Currently, I am working on the verification of Memory Subsystem Clock gating architecture in GPU Power arch verification leveraging Nvidia's highly automated and scalable DV infrastructure. Earlier, I had developed verification testbench and TB infra for Distributed Virtual Memory (DVM) unit verification that follows AMBA CHI DVM protocol to communicate between DVM and NOC (Network on chip). I also got opportunity to work on functional and coverage driven verification for CPU Clocks (in both unit and subsystem level) where I developed SV/UVM based testbenches, enhance my debugging skill through test regression debug and functional and code coverage closure. Completed MTech from National Institute of Calicut with CGPA 8.68. Have knowledge on C, C++, Verilog, SV, UVM, AMBA, CHI, AXI, Python, Perl, TCL, UNIX, TB Infra Area of interest: Computer Architecture, Digital System Design and verification.

Experience

5 yrs 11 mos
Total Experience
5 yrs 11 mos
Average Tenure
5 yrs 11 mos
Current Experience

Nvidia

3 roles

Senior Design Verification Engineer

Jun 2023Present · 3 yrs

Test PlanningFormal VerificationRTL VerificationSystem on a Chip (SoC)DebuggingSystemVerilog+9

Hardware Design Verification Engineer

Jul 2020Jun 2023 · 2 yrs 11 mos

Test PlanningFunctional Verification

Design Verification Intern

May 2019Jul 2020 · 1 yr 2 mos

RTL VerificationUniversal Verification Methodology (UVM)

Education

National Institute of Technology Calicut

Master of Technology - MTech — Electronics design and Technology

Jan 2018Jan 2020

Meghnad Saha Institute Of Technology(MSIT)

Bachelor of Technology - BTech — Electronics and Communication Engineering

Aug 2012May 2016

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