Rohith K — Software Engineer

ASIC Design Verification Engineer with over five years of professional experience in the semiconductor domain, specialized in design and verification across SoC, subsystem, and IP levels, Gate-level simulations (GLS), delivering high-quality, coverage-driven verification solutions. Skills: • IP, SS and SoC verification. • DV Plan creation to cover all features, execution and end to end DV closure. • SystemVerilog-UVM Testbench environment bring up from scratch, bug analysis and debugging skills. • Hands-on with Register Abstraction Layer (RAL) models and third-party vendor VIPs integration. • Debug regression failures, identify root cause, log and communicate the issue, validate the fix, and promote the changes to full regression. • Gate-level simulations (GLS) on PNR and synthesis netlist with SDF annotations and debugging. • Coverage plan creation, Code and Functional coverage analysis and closure. • Protocols: AMBA protocols – AXI, APB, AHB; UART, SPI. • Scripting: Perl and Python. • Tools: Cadence Xcelium, SimVision, IMC, Synopsys VCS, Verdi, Questa Sim. Perforce, Methodics, GitHub Copilot, VS Code. Responsibilities Held: • AI Hardware Accelerator (NVDLA) - IP, SoC DV • Peripherals Verification - SoC DV • 5G ORAN DLOP - Subsystem, GLS, SoC DV • 5G ORAN FHPP - Subsystem Stats DV • Network Peripherals - Subsystem, SoC DV • VIP Integration - Cadence AXI, APB, AHB, SPI; SmartDV SPI • DSP Core - DL LPHY DUC - Subsystem DV • RISC-V Core Debug Module Verification using JTAG Interface • AXI4, UART - IP DV • CRC error detection - IP DV • Successfully contributed to verification deliverables for two full product-level tape-outs.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SoC and IP verification.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 6 mos