J

Jairaj Mirashi

Product Engineer

Bengaluru, Karnataka, India4 yrs 6 mos experience

Key Highlights

  • Expert in Design Verification with strong UVM knowledge.
  • Proficient in high-speed bus protocols and digital electronics.
  • Strong problem-solving and communication skills.
Stackforce AI infers this person is a Design Verification Engineer in the Semiconductor industry.

Contact

Skills

Core Skills

Design VerificationSystemverilog

Other Skills

PCIeEthernetUVMUniversal Verification Methodology (UVM)AHBAPBUARTCommunicationDigital DesignsCC++LinuxMATLABDebuggingTeamwork

About

Since my early days, I've been captivated by the fascinating world of digital electronics and the power of 1's and 0's. Driven by a desire for positive logic, I strive to work smart with unwavering dedication to achieve both personal and professional goals Technical Skills: • HDL/HVL: Verilog, SystemVerilog • Verification Methodology: UVM • Other Languages: C, C++ • Protocol Knowledge: AHB, APB, UART, SPI • Operating System: Linux Core Competencies: • Creating Test Plans and Writing Test Cases • Functional Coverage and Code Coverage • Regression Testing • Developing Testbenches (TB) and TB Components for Block-Level Verification Key Strengths: • Strong understanding of verification methodologies and best practices • Strong problem-solving skills • Strong written and verbal communication skills Behavioral Skills: • Organized • Time Management • Team Player • Motivated

Experience

4 yrs 6 mos
Total Experience
--
Average Tenure
--
Current Experience

Appex semiconductor pvt ltd

Design Verification Engineer

Sep 2024Present · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

  • Worked on PCIe Gen5 DLL, 25G Ethernet MAC, and 10G/25G PCS verification.
  • Experience in writing test plans, test cases, functional coverage, and debugging.
  • Verified flow control, replay logic, BER monitoring, and error scenarios.
  • Followed IEEE 802.3 and PCIe 5.0 specs for compliance.
  • Hands-on with SystemVerilog, UVM, and industry-standard tools like VCS.
PCIeEthernetDesign VerificationSystemVerilog

Ust

Design and Verification Engineer

May 2022Sep 2024 · 2 yrs 4 mos · Bengaluru, Karnataka, India

  • Good knowledge in System Verilog and UVM methodology.
  • Worked on high-speed bus protocols like AHB, and low- performance APB bus.
  • Worked on UART IP core compatible with WISHBONE interface.
  • Worked on SPI Controller core compatible with WISHBONE interface and SPI protocol.
  • Having hands-on experience in, creating Test plans, writing Test cases, Functional Coverage, Code coverage, and regression.
  • Worked on developing TB &TB components for blocklevel verification.
  • Good coding skills for Verification and hands-on with industry-standard simulators such as Questa-sim used in Verification and waveform-based debugging tools.
SystemVerilogUniversal Verification Methodology (UVM)Design Verification

Maven silicon

Trainee

Nov 2021Apr 2022 · 5 mos · Bengaluru, Karnataka, India

CommunicationDigital Designs

Education

KLE Technological University - Hubballi (India)

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2017Jan 2021

Alva's College of Education

Pre University — Computer Science

Aug 2015May 2017

Stackforce found 100+ more professionals with Design Verification & Systemverilog

Explore similar profiles based on matching skills and experience