Venkatesh Rathod — Software Engineer
Working at Moschip Semiconductor industry as DFT Engineer Performed scan insertion and scan compression Performed ATPG stuck-at and transition fault pattern generation Performed Synthesis and done validation of timing constraints (SDC) Worked with the designers to correct unacceptable Verilog constructs Provided feedback and guided the designers to fix scan controllability/observability issues Timing analysis using ZWL before handing off the netlist to PNR Verified RTL code with synthesized netlist using Conformal
Stackforce AI infers this person is a DFT Engineer specializing in semiconductor design and verification.
Location: Hyderabad, Telangana, India
Experience: 5 yrs
Skills
- Dft
- Logic Synthesis
Career Highlights
- 5+ years of experience in DFT engineering.
- Expert in scan insertion and ATPG.
- Strong background in timing analysis and RTL verification.
Work Experience
MosChip®
Senior DFT Engineer (8 mos)
Engineer-DFT (5 yrs)
Education
Master of Technology - MTech at National Institute of Technology, Tiruchirappalli
Bachelor of Technology - BTech at Geethanjali College of Engineering and Technology
12 at Jawahar Navodaya Vidyalaya - JNV
