Abhishek Jain

DevOps Engineer

Bengaluru, Karnataka, India16 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL verification and ASIC design methodologies.
Proficient in multiple hardware description languages.
Led verification projects for advanced semiconductor technologies.

Stackforce AI infers this person is a semiconductor verification expert with extensive experience in ASIC and RTL methodologies.

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Skills

Core Skills

Rtl VerificationVerification LeadVerification EngineerSoc VerificationPower ValidationIntern

Other Skills

VerilogUvmVHDLGLSUPFApplication-Specific Integrated Circuits (ASIC)Low-power DesignDebuggingC (Programming Language)C++C#Python (Programming Language)PerlSystemVerilogVery-Large-Scale Integration (VLSI)

About

Register Transfer Level (RTL) based logic modelling using Hardware Descriptive language (HDL) Design and verification methodology using hardware description and verification languages (HDVLs) ASIC design methodology Integrated circuit design-for-test-techniques, semiconductor fabrication processes CMOS processing technology, CMOS layout, circuit design and logic design Analog and Mixed Signal Integrated Circuit Design, differential amplifiers, operational amplifier design Microprocessor based computer system, Static Power validation Specialties: Languages: Verilog HDL, SystemVerilog, VHDL, C, C++, VB.NET, Perl, ASM [8086/8051], UNIX Tools/Packages: Xilinx ISE, Mentor Graphics, Modelsim, L-Edit, Matlab, Multisim, Atrenta Spyglass LP

Experience

16 yrs 1 mo

Total Experience

4 yrs

Average Tenure

8 yrs 1 mo

Current Experience

Intel corporation

2 roles

Verification Lead

Promoted

May 2021 – Present · 5 yrs 1 mo

Working on CXL, smartnic, transceivers(UX and Barak).

VerilogUvmRTL VerificationVerification Lead

Sr Product Verification Engineer

May 2018 – May 2021 · 3 yrs

Working on CXL, smartnic, transceivers(UX and Barak).

RTL VerificationVHDLVerification Engineer

Microsemi corporation

Sr Product Verification Engineer

Jan 2016 – May 2018 · 2 yrs 4 mos · Bengaluru Area, India

Worked on verification PCIE_SW/expander series.
Different PCIE_SW module/feature testing using specmanE.
DDR4 memory controller

RTL VerificationVHDLVerification Engineer

Pmc-sierra

Product Verification Engineer

Feb 2011 – Jan 2016 · 4 yrs 11 mos · Bengaluru Area, India

Doing verification of an SoC at top level and module level using Specman including expanders and controller series from PMC. Worked on PCIE, I2C, SAS/SATA, AXI protocols.
Currently working on verification PCIE_SW/expander series. different module/feature testing using specmanE.
Worked on GLS realted to different project.
Completely owned and semi-designed the Testbench for I2C.
Worked on the Subsystem level verification for the PCIe controller, Extss_12G, SXP expander series.

RTL VerificationVHDLSoC VerificationVerification Engineer

Intel corporation

Intern

Sep 2009 – Jun 2010 · 9 mos

I did Power validation for Intel first 32 nm SoC using Atrenta’s Spyglass LP tool. Here I own the static power validation for entire south cluster. Prepared power intent (UPF and sgdc) file for complete south cluster. Wrote scripts to analysis the netlist and to automate the entire environment.
Worked on Synopsis dollar_power tool for dynamic Power validation
During this project I have to evaluate the Spyglass LP tool, and validate the design using the same tool. Here I required to validate that all the signals are properly isolated and level shifted when moving between different power domains. Output of power domain should attain a known value when power gating is applied.
At the post- layout netlist all the Standard cells including power switches, isolation cell, etc are connected to proper supply and enable signals.
Wrote some scripts to check the consistency of Spyglass LP results.

RTL VerificationVHDLPower ValidationIntern