Achyuth Narla

Software Engineer

Hyderabad, Telangana, India11 yrs 6 mos experience

Highly Stable

Key Highlights

Expertise in ASIC Physical Design and Verification.
Led 16 successful tape-out deliverables across multiple technology nodes.
Strong collaboration with cross-functional teams for design quality.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC Physical Design and Verification.

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Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Clock Tree SynthesisPower OptimizationSoCFloor planningPlace-and-route implementationTiming/power/area optimizationDRC correlationCAD automationPhysical VerificationDRC rulesCutting edge technologiesChip design layoutDebugBlock level implementationPower planning

About

My Career in VLSI started with the FINFET Technology 14nm . Have Strong Background of ASIC Physical design : Floor planning and PNR . Expertise in the Physical Verification for Block , Wrapper and Full chip Level . Part of 16 Successful Tape-out deliverable's (two 3nm, two 5nm, five 7nm projects , three 10nm and two 14nm and one 11nm ,8nm technology nodes). Executed complex design blocks, operating at high frequency in 7nm & 5nm TSMC . Worked on the physical design from synthesis to tapeout and the full chip finishing for 6 various projects till tape out.

Experience

11 yrs 6 mos

Total Experience

1 yr 11 mos

Average Tenure

1 yr 7 mos

Current Experience

Sandisk

Principal Engineer

Nov 2024 – Present · 1 yr 7 mos · Hyderabad · Hybrid

I am an experienced Physical Design Engineer specializing in subsystem and block‑level ownership of low‑power, high‑performance ASIC designs. My expertise spans end‑to‑end floorplanning, place-and-route implementation, timing/power/area optimization, and advanced debug strategies for complex SoCs.
I drive PNR execution with a strong focus on quality, convergence, and predictability—ensuring robust design closure and on‑time delivery. I bring deep proficiency in clock tree analysis, timing ECOs, and full‑chip timing convergence, with a track record of resolving critical‑path bottlenecks and achieving aggressive performance targets.
I closely collaborate with RTL, DFT, verification, and integration teams to streamline design handoffs, refine constraints, and strengthen upstream design quality. I also lead IP integration strategies that minimize schedule risk and ensure silicon‑proven, high‑reliability ASICs.
Core Strengths:
Subsystem/Block-level floorplanning & PnR ownership
Timing closure, STA debug & power/performance/area optimization
Clock tree design, analysis & ECO flow management
Cross-functional collaboration with RTL, DFT, PD & verification teams
IP integration, physical signoff & convergence strategies
Hands-on experience driving design from early architecture to tapeout
I’m passionate about building power-efficient, scalable, and high‑quality silicon and continuously improving physical design flows to achieve first-time-right execution.

Physical DesignTiming ClosureClock Tree SynthesisPower OptimizationSoC

Intel corporation

System-on-Chip Design Engineer

Feb 2020 – Oct 2024 · 4 yrs 8 mos · Hyderabad, Telangana, India

Amd

2 roles

Senior Silicon Design Engineer

Promoted

Mar 2019 – Jan 2020 · 10 mos

Senior Silicon Design Engineer for Client SoC's at AMD Hyd. Responsible for driving process improvements like early DRC correlation with PnR tools, Parallel DRC/LVS convergence methodology, engineering DRC decks, CAD automation scripts to improve productivity of the team. As a Senior Engineer am mainly responsible for PD teams to achieve best convergence with respect to physical verification . Also responsible for all block level Physical Verification sign-off and Full chip.

DRC correlationCAD automationPhysical VerificationPhysical Design

Physical Design Engineer

Apr 2018 – Mar 2019 · 11 mos

Qualcomm

Physical Design Engineer

Mar 2017 – Mar 2018 · 1 yr

Physical Design Engineer for block level for various projects at Qualcomm Bangalore.
Physical verification for understanding 7nm DRC rules and help QCT . Worked on various cutting edge technologies for TSMC -10nm, 7nm, SAMSUNG - 11nm,8nm .

Physical VerificationDRC rulesCutting edge technologiesPhysical Design

Intel corporation

Physical Design Engineer

Mar 2015 – Mar 2017 · 2 yrs · Bengaluru Area, India

Creates bottoms-up elements of chip design layout including Transistor, cell, and block-level custom layouts, FUB-level floor plans, abstract view generation, RC extraction, and schematic-to-layout Verification, physical verification and debug using phases of physical design development

Chip design layoutPhysical verificationDebugPhysical Design

Nanochip solutions pvt. ltd.

VLSI engineer

Aug 2014 – Feb 2015 · 6 mos · Greater Bengaluru Area

I had undergone a industry training from RV in the field of Backend (physical Design). As a part of training I have done Block level implementation in IC Compiler from synopsys. Through the training have done AP&R, power planning, congestion control placement , Timing closure , physical verification.

Block level implementationPower planningTiming closurePhysical Design