Hargovind Sahu

Software Engineer

Bengaluru, Karnataka, India18 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in RTL design and architecture.
Proficient in multiple on-chip communication protocols.
Experienced in developing verification environments for FPGA.

Stackforce AI infers this person is a Semiconductor expert with a focus on RTL design and verification.

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Skills

Core Skills

SystemverilogOn-chip Communication ProtocolsDigital Ip DevelopmentFpga ValidationEmulation TechniquesVerification Environment Development

Other Skills

C (Programming Language)FPGAStatic Timing AnalysisEmulationLogic SynthesisJTAGCDCFPGA memoryFPGA DSPEmulatorHVLDPIFIFOAssertionsFunctional Testing

About

Having experience in RTL design and architecture, synthesizable Verification IP, and Digital IP. Experience with coherency protocols (AMBA-CHI) and other on-chip communication protocols like AXI, AXI4stream, AHB, APB (Created various transactors for protocol. Expertise Verilog HDL design, System Verilog, C++/C, UVM, and System-Verilog based Test environment development using OPPS concept.

Experience

18 yrs 8 mos

Total Experience

5 yrs

Average Tenure

3 yrs 6 mos

Current Experience

Arm

Principal Engineer

Dec 2022 – Present · 3 yrs 6 mos · Bengaluru, Karnataka, India

Siemens eda (siemens digital industries software)

3 roles

LMCS

Promoted

Jan 2021 – Dec 2022 · 1 yr 11 mos · Noida, Uttar Pradesh, India

Created synthesizable transactor for on-chip communication protocol (AMBA CHI, AXI4stream, APB )
Created Cache controller for CHI which could generate Snoop responses that are configurable by the user interface

SystemVerilogC (Programming Language)On-chip communication protocols

MCS

Aug 2017 – Jan 2021 · 3 yrs 5 mos · Noida, Uttar Pradesh, India

LMTS

Nov 2012 – Jul 2017 · 4 yrs 8 mos · Noida, Uttar Pradesh, India

Created Digital IP for validation/Debugging at the design speed of any IP/System/subsystem running on FPGA

FPGAStatic Timing AnalysisDigital IP DevelopmentFPGA Validation

Mirafra technologies

Senior R&D Engineer

Sep 2011 – Nov 2012 · 1 yr 2 mos · Bengaluru Area, India

Validated Hierarchical referencing of signal in Assertions for Zebu Emulator.
Validated SVA support inside Process loop and Process Block for Zebu Emulator.

EmulationFPGAEmulation TechniquesFPGA Validation

Nec india

2 roles

Module Lead

Jul 2009 – Aug 2011 · 2 yrs 1 mo

MTS

Jul 2007 – Jun 2009 · 1 yr 11 mos

Created System Verilog based Verification Environment for validation of small size designs
IP Design Validation on FPGA (Xilinx), using ChipScope
Validated the HSL for Synthesizable Verilog code generation and functional Validation on simulation on FPGA

SystemVerilogC (Programming Language)Verification Environment DevelopmentFPGA Validation