Adithyan J

Product Engineer

Yokohama, Kanagawa, Japan4 yrs 10 mos experience

Key Highlights

Expertise in ASIC Physical Design across advanced technologies.
Proven track record in CPU design and static timing analysis.
Continuous learning through MTech studies in Microelectronics.

Stackforce AI infers this person is a Semiconductor Engineering professional with a focus on ASIC Physical Design and CPU architecture.

Contact

Skills

Core Skills

Asic Physical DesignStatic Timing AnalysisCpu Physical DesignPlace And Route

Other Skills

Logic SynthesisPhysical SynthesisFloor PlanningLayoutTroubleshootingPNRFloorplanFusion CompilerPrimetimeRedhawkHikingECOMulti clock tree buildingLogical Equivalency TestEMIR

About

Currently I am working in techmahindra limited with the latest product of Socionext. Here I am handling PNR and STA of the block. Previously I was working in CPU design, focusing working in advanced 3nm technology. In the midst of my MTech studies in Microelectronics at BITS Pilani. I contribute to the critical timing section of high-performance 5 GHz CPUs. This dual commitment to education and hands-on experience embodies my pursuit of continuous learning and professional excellence. Previously with Tech Mahindra Limited, our work on various blocks spanning STA to ECO flows honed my expertise in ASIC Physical Design across 3nm to 7nm technologies. The journey from a starting engineer to block/full chip owner showcases my growth, driven by a passion for technology and a vision to remain at the cutting edge of the semiconductor industry. I love my current job and can go upto any limit to full fill the tasks assigned to me. And I love what I do.

Experience

4 yrs 10 mos

Total Experience

1 yr 8 mos

Average Tenure

1 yr 6 mos

Current Experience

Tech mahindra

Engineer at Socionext, Japan

Dec 2024 – Present · 1 yr 6 mos · Tokyo, Japan · On-site

I am working on backend development/ IC design on chips: 7nm,5nm technologies.
Location: Shin Yokohama
Tools: Innovus.
Daily work involves place and route, STA, writing useful scripts to the clients.
I am also working on MSCTS, Floor planning, Engineering Change Order, STA.

Logic SynthesisPhysical SynthesisPlace and RouteStatic Timing AnalysisFloor PlanningASIC Physical Design

Sintegra inc.

Physical Design Engineer at Google, taiwan

Oct 2023 – Dec 2024 · 1 yr 2 mos · Taipei, Taipei City, Taiwan · On-site

Worked as CPU physical design for Google in Taiwan
Worked on CPU cache unit and also in STA front end feedback to RTL team, also did a lot of floorplans.
Location: Banqiao, Taiwan
Client: Google
Tools: Innovus, primetime, Redhawk sc.
Got recommendation letter from this employer.

LayoutTroubleshootingStatic Timing AnalysisFloor PlanningCPU Physical Design

Tech mahindra cerium pvt ltd

Engineer Physical Design

Aug 2021 – Oct 2023 · 2 yrs 2 mos

Physical design on production & test chips: 3nm,5nm,16nm technologies.
Location: Kochi
Client: Intel, TSMC
Tools: Fusion compiler, primetime, formality, Redhawk, Redhawk SC.
Promoted to Engineer position within 2 years in the same company and received Pat on the back award from Tech Mahindra.

PNRFloorplanFusion CompilerPrimetimeRedhawkASIC Physical Design+1