Jan 2017 – Jun 2017 · 5 mos · Bengaluru, Karnataka, India

• Title: ECO Cycle Reduction for IO Timing Closure of an SoC.
• Tools/Software Used: PrimeTime (Synopsys), Tweaker (Dorado), Infineon In-House Design Flow.
• Scripting Language Used: Tcl.
• Area of Work: As an Intern with the SoC Design Flow Group, Physical Design & Methodology Team, Following is an Overview of the Process-Flow executed:
• Understanding the ASIC Design Cycle & Static Timing Analysis for Nanometer Design.
• Gaining Protocol Level Overview of IO Interfaces.
• Extensive Coverage/Analysis of Constraints written for Individual IO Interface.
• Generation of Scenario Specific IO Timing Reports using PT Distributed Multi-Scenario Analysis.
• ECO Generation using Tweaker tool --> ECO Analysis/Incorporation --> Slack Violations Fix/Interface Timing Closure.
• Comparison of Previously Violated & Presently Fixed Timing Reports Establishing Merit of Proposed Methodology.

Mar 2016 – May 2017 · 1 yr 2 mos · Ranchi, Jharkhand, India

• As a Member of the 2016-17 Placement Committee, I was responsible for efficiently creating/managing Placement Opportunities/Activities of ECE-2017 Graduating Batch & Internship Activities of ECE-2018 Graduating Batch, alongside 900 UG/PG students of BIT Mesra. My core responsibilities included:
• o Connecting with Talent Acquisition Leads from various sectors viz. Core/Infrastructure/PSU, Consultancy/Analytics, Electronics/Telecom/Energy/Automotive, IT, FMCG, Pharmaceuticals, Banking/BFSC etc. and employment firms of national and international repute.
• o Inviting Companies to Participate in Campus Hiring Events & Explore the BIT Mesra Talent Pool for their Organisational Requirements.
• o Managing Hiring Events from the root level, comprising of Hospitality Arrangements for the University Hiring Team at Campus, Conducting Online/Written Tests followed by Group Discussions/Personal Interviews to Offer Rollouts to Final Selectees.
• o Fostering Long-Lasting Relationship Development through Participation in Various Student Engagement Programs, Conducting Promotional Workshops/Hackathons etc.
• Achievements:
• o Instrumental in Mapping the following companies for their 1st Participation and Incorporation in the BIT Mesra Placement Cycle.
• Qualcomm
• MediaTek
• Samsung Research Institute - SRI Delhi
• Samsung Research Institute - SRI Bangalore
• Infineon Technologies
• TATA Communications
• Capgemini SE
• Blackrock India

May 2015 – Aug 2015 · 3 mos · Thin-Film Nano-Technology Lab, Chang Gung University, Tao-Yuan, Taiwan

• Title: Variable Pulse Generator Design for Read Endurance & Pulse Endurance in Memory Devices (RRAM and CBRAM Devices)
• Tools/Software Used: Cadence Simulation Software.
• Area of Work: Following was the Process-Flow-Chart Implemented:
• o Software Level Design/Implementation of Target with the following expected features:
• o Desired Waveform Pattern consists of a Program Pulse -> Read Pulse -> Erase Pulse -> Read Pulse.
• o User Configurable Amplitude & Frequency of Pulse Train.
• o Pulse Count Calculation for Stress Estimation on the Memory Device.
• o Verification of Proposed Design on a PCB Board for Merit Analysis.
• o Exposure to Nano-meter Level Fabrication Methodologies, MOS Transistors, Capacitors and Memory Device Fabrication.

Jun 2014 – Aug 2014 · 2 mos · Durgapur, West Bengal, India

• As a Project Trainee with VLSI Design Lab of NIT Durgapur, I have gone through the Cadence ADE Design Flow, covering both design, simulation, layout & floor-planning. My training involved the following:
• o Introduction to Complete Product Design Cycle: Concept /Specification --> Architecture --> Schematics --> Layout --> Release --> Silicon Debug --> Final Release.
• o Familiarity with IC Design Tools/Simulators, IC Layout Design, Techniques, and Verification Methodologies.
• o Gaining Expertise in RF/Analog Circuit design in sub-90nm CMOS Technology Node.
• o Experience with Front-End RF and Analog Circuit Blocks such as LNAs, Oscillators, Frequency Synthesizers/Phase Lock Loops (PLLs), ADC/DAC and Filter Design.
• o Learning RF Digital Communication, Modulation, Noise & Linearity Concepts.

May 2014 – May 2017 · 3 yrs · Birla Institute of Technology, Mesra, Ranchi, Jharkhand-835215

• + Research Publications:
• + Paper Title: Impact of Voltage and Temperature Variations on the Q-Factor of CMOS Active Inductors. (3rd International Conference on Microelectronics, Circuits and Systems, Micro2017)
• Authors: Agnish Mal, Yashdeep Singh, Ankan Dutta, Vikash Kumar, B.B. Pal and Dr. Aminul Islam
• + Paper Title: Compact 6T Design of Voltage Controlled Tunable Resistor for High Frequency Applications. (2nd International Conference on Devices for Integrated Circuit DevIC 2017)
• Authors: Agnish Mal, Rishab Mehra, Amit Krishna Dwivedi and Dr. Aminul Islam
• + Paper Title: Amplifier Design Approximations in Sub-Micron CMOS. (International Conference on Microelectronics, Computing and Communication (MicroCom 2016) Sponsored by IEEE)
• Authors: Agnish Mal and Dr. Ashis Kumar Mal
• + Paper Title: A Comparative Analysis of Various Programmable Delay Elements using Predictive Technology Model. (International Conference on Microelectronics, Computing and Communication (MicroCom 2016) Sponsored by IEEE)
• Authors: Agnish Mal, Amit Krishna Dwivedi and Dr. Aminul Islam
• + Paper Title: CMOS Based Compact Wide Band Tunable Inductor Design. (IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems (ICIIECS’15)
• Authors: Agnish Mal, Rishab Mehra, Amit Krishna Dwivedi and Dr. Aminul Islam
• + Paper Title: CMOS Amplifier Design Using Simplified gm/Id Technique. (1st International Conference on Intelligent Computing & Application (ICICA-2014)
• Authors: Agnish Mal and Dr. Ashis Kumar Mal
• + Paper Title: Simulator Assisted CMOS Amplifier Design Using alpha-power MOS Model. (IEEE Sponsored International Conference On Devices, Circuits And Communications ICDCCom-2014)
• Authors: Agnish Mal and Dr. Ashis Kumar Mal