Jun 2016 – Mar 2018 · 1 yr 9 mos · Hyderabad Area, India

Jun 2015 – May 2016 · 11 mos

• My domain of internship is Standard cell design and libraries development in 28nm (FDSOI) and 40nm technology. This domain includes drawing schematics, layouts for cells with different architectures.Performing area and delay optimization for a given Standard cell library. Analysis of the delay, power dissipation of such cells.

Jun 2015 – May 2016 · 11 mos

• Responsibilities as Standard Cell design intern:
• 1.Current working on ULV (Ultra low voltage) platform :
• i) Analyse effect of delay variability using ELDO on :
• Combinational cells
• Clock libraries ( BF and IV )
• 2. Logic optimization of combinational cells such as AOI or OAI etc of various libraries for
• comparison of speed ,area and power.
• 3. Check for delay balancing of Clock library cells.
• 4. Analysis of SCAN D flip flop:
• i) Analyze HOLD TIME of SCAN flop is sensitive to which set of transistors.
• ii)Calculate SETUP TIME of SCAN flop and figure out ways to reduce SETUP time of Flop
• 5.Performing Functional Validation of libraries.
• 6.Performing Pre-characterisation of libraries .
• 7.Development of layouts of standard cells in CADENCE VIRTUOSO environment.
• 8.INTEGRATION and PACKAGING of standard cell libraries.
• i) MIGRATION of layouts for different threshold and poly bias.
• ii) Development of different Layout views.
• iii) RC extraction using PLS Kit and RC-XTRACT tool.
• iv) Performing DRC, LVS, CHK, DFM, SRD checks, etc using MENTOR CALIBRE tool.
• 9.CO-VALIDATION of standard cell libraries.
• i) Development of ABUTMENT database of libraries using ediplace CADENCE ENCOUNTER
• ii) Running LFD, OPC checks on abutment database.