Eashwar Raghuraman — Product Engineer
Experienced Circuit design engineer with focus on timing, power, noise aspects and post silicon speed path debug of custom data path blocks. Self-motivated with strong focus on innovation reflecting in 1 circuit innovation approval for patent filing, 2 DTTC (internal to Intel) papers accepted for publication and winner of Intel India site level ideation challenge for the year 2018 * 3 Industrial Publications * 1 US Patent Grant - Custom Circuit Design (Logic Optimization, Placement, Routing , Partitioning) - Timing Analysis (High Frequency Latch Based Designs) - Post Silicon Debug of Timing Failures - Back End Low Power - Thermal and Reliability (signal and power electro-migration, TDDB, Aging , SER) - ML for VLSI
Stackforce AI infers this person is a VLSI Design Engineer with expertise in custom circuit design and low power methodologies.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 10 mos
Skills
- Machine Learning
- Power Modelling
- Custom Circuit Design
- Timing Analysis
- Low Power Design
Career Highlights
- Patent grant for innovative circuit design.
- Published multiple papers in internal forums.
- Winner of Intel India ideation challenge 2018.
Work Experience
Qualcomm
Power Modelling and Sign Off Modem Core (6 yrs)
Intel Corporation
CPU Core Digital Circuit Design Engineer (4 yrs 1 mo)
MediaTek
Everyday Genius Internship and Master Thesis (9 mos)
Education
Master's Degree at Nanyang Technological University Singapore
Master's Degree at Technical University of Munich
Bachelor's Degree at National Institute of Technology, Tiruchirappalli
