Arun Chaudhary

Software Engineer

Ghaziabad, Uttar Pradesh, India11 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in FPGA design and verification.
Hands-on experience with multiple FPGA platforms.
Proficient in RTL design for high-speed Ethernet IP.

Stackforce AI infers this person is a skilled FPGA and RTL design engineer in the semiconductor industry.

Contact

Skills

Core Skills

Rtl DesignFpga

Other Skills

25G40G10GVCSVerdiSpyglassQuartus PrimeZynqMpsoczedboardAC701KintexXilinx VivadoSDKSynopsys toolsC++

About

Hi,I am Arun ,Electronics And Communication Engineering Graduate. Trained FPGA RTL Design And Verification . Having good knowledge in Digital Design ,Hardware Language and scripting . Knowledge of design creation using Vivado ,Quartus using stratix 10,Agilex ,Zynq,Zedboard ,Vertext ,kintext . Exploring new tools for CDC and Lint - Synopsis Spyglass Design tool - Intel quartus software prime Working with - 1G /10G 40 G and 100G ethernet ip RTL FPGA DESIGN ENGINEER Currently working on the project of 4k video processing ...

Experience

11 yrs 2 mos

Total Experience

2 yrs 9 mos

Average Tenure

3 yrs 6 mos

Current Experience

Amd

Silicon Design Engineer

Dec 2022 – Present · 3 yrs 5 mos · Hyderabad, Telangana, India · On-site

Contractor

Cerium systems (worked in client intel )

Sr.Design Engineer

Oct 2021 – Dec 2022 · 1 yr 2 mos · Bangalore Urban, Karnataka, India · On-site

worked on 25G, 40G, 10G in the intel client as RTL design engineer, experience with vcs , verdi , spyglass and Quartus prime.

25G40G10GRTL designVCSVerdi+3

Aujus technology private limited

FPGA RTL DESIGN ENGINEER

Sep 2018 – Oct 2021 · 3 yrs 1 mo · Noida, Uttar Pradesh, India

worked on ZynqMpsoc , zedboard ,AC701, Kintex ( xilinx vivado),SDK

ZynqMpsoczedboardAC701KintexXilinx VivadoSDK+2

Pine training academy

Trainee

Jan 2017 – Jun 2018 · 1 yr 5 mos · Noida Area, India

I had done my internship in the pine training academy in the front end FPGA design engineer from January 2017 to July 2018. I did a project on the video and image processing

Chitkara university

2 roles

Student

Aug 2014 – Jan 2018 · 3 yrs 5 mos

I completed my graduation from chitkara university Himachal parades, baddi

Student

Aug 2014 – Jul 2017 · 2 yrs 11 mos

projects:
1. Text scroll in seven segment: ( March ,2017)
I have made the text scrolling project on the Nexys 4DDR Artix-7 FPGA Board,I initially case1.prints HELLOCUA(hello Chitkara university arun my name),case2. HELOCUHP(hello Chitkara University Himachal Pradesh), HELOFPGA and then then it starts scrolling all the text.
2. 00 to 99 two Digit Decimal counter . ( Feb,2017)
Artix7 board has the 100Mhz clock signal ,I used the 1 second delay for the each bit to display. for the counting up to 100000000hz , I made the 27 bit counter , Here I am going to make a 2 digit counter that counts from 00 to 99 and then rolls over back to 00. The counter will increment every 0.1 second. The 0.1 second interval is produced by another counter that will produce an enable tick every 0.1 second to increment our main counter.
3. Traffic light controller (July 2017)
I have made the four way traffic light controller on FPGA artix-7 board ,I initialize the each pair of the segment with initial counter value 90:60:30:30 ,when start button made logic high every counter start decreamenting , when the last seg ie.30 reaches to the 05 it changes to the yellow light ,again after 5 sec it changes to the red for the 25 sec respectively the pattern is follow.