Dec 2017 – Jun 2018 · 6 mos · Bengaluru Area, India

• +Worked as Digital design engineer for WTR/RF ICs. This involved designing micro-architecture based on analog parts and wireless protocol requirements.
• +Worked on PLDRC, CDC, Synthesis, FV and STA for delivering quality RTL
• +Wireless communications systems and standards understanding for LTE-CAT, NB-IOT, GSM, as per requirement of baseband modem and implementation of synthesizer, UL/DL paths, etc.

Jul 2016 – Nov 2017 · 1 yr 4 mos · Bengaluru Area, India

• +Worked on SOC Design Verification for SPI, I2C, I3C, UART, SPI Slave and IP Accelerator.
• +Gained knowledge on SOC and CPU Architecture
• +Worked closely with design and micro-architecture teams to understand the functional and performance goals of the design
• +Worked to develop a comprehensive verification plan. Review specifications, develop attributes, tests and coverage plans, define methodology and test benches
• +Worked on gate level functional verification, analysing code and functional coverage
• +Worked on ATE functional test pattern generation for logic testers
• +Integrated new VIP in SOC Verification environment

May 2015 – Jul 2015 · 2 mos · Los Angeles

• Worked under Prof. Peter Beerel to build Low Power Digital to Analog Converter for fine grained Programmable Delay Element which could be used in asynchronous VLSI systems.

Jan 2014 – May 2016 · 2 yrs 4 mos · Hyderabad Area, India

• VLSI Architectures, Spring 2016
• Linear Electronics Circuits, Monsoon 2015
• Introduction to VLSI, Spring 2015
• Digital Logic and Processors, Monsoon 2014
• Basic Electronics Circuits, Spring 2014