Jul 2023 – Mar 2026 · 2 yrs 8 mos · On-site

• Driving the development of agentic flow formal verification with a focus on streamlining collateral generation, minimizing complexity, and achieving broader coverage.
• Working on formal property generation using LLMs, extended with a custom RAG pipeline for improved retrieval and fine-tuning
• Formally verified AHB bus matrix
• Working on Retention Sufficiency flow for power aware design
• Working on enhancement of Connectivity Check for memory redundancy, fuse, hardware events and core power reduction at subsystem level
• Enhancement of Reverse connectivity flow
• Developed a command TCL parser for seamless conversion from VC-Formal to JasperGold and vise versa

Jul 2022 – Jun 2023 · 11 mos · On-site

• Developed AI based optimization frame work for post silicon characterization of RF transceiver, to reduce test time by optimizing multiple register bias combinations.
• Developed a signal noise removal autoencoder using keras, that can be used to eliminate the measurement artifacts.
• Developed a framework to analyze and cluster 30 part ATE data to identify the DLPs and offsets that can be removed from screen program to save test time with 0% risk.
• Enabled RF PCB Layout Optimization through Genetic Algorithm.

May 2020 – Aug 2020 · 3 mos · Remote

• The WARP-V RISC-V core generator was developed in 2018, it is the most-configurable, most-adaptable open-source RISC-V CPU core generator, taking advantage of advanced digital design features of TL-Verilog. Till now WARP-V has support for RV32I base instruction set architecture and is formally verified using Risc-V formal. Now I am implementing RV32F(Single Precision Floating-point) Unit extensions to the Warp-V core by using a "hard float by Berkeley" library written in verilog, which also supports IEEE 754 single-precision floating-point unit. My next target is to introduce Virtual Memory support (TLB) in Warp-V.

Jun 2018 – Jul 2018 · 1 mo · Durgapur, West Bengal, India

• A high speed high speed VLSI design of the USG back-end unit is designed for the non-stationery organs like the heart.To prototype these units an FPGA platform is used. Massive usage of the parallel - pipelining technique has helped in achieving high throughput at low power. The Digital scan conversion architecture operates at 14.66 MHz and is capable of scan converting 132 raw frames per second. Similarly, the Speckle Reduction Imaging unit operates at 221 MHz and is capable of de-speckling images of size 640 9 480 at 698 fps. . With this model, it is possible to investigate objects without motion blur using these units.