Oct 2023 – Jun 2025 · 1 yr 8 mos · Bengaluru, Karnataka, India · On-site

Jun 2018 – Sep 2023 · 5 yrs 3 mos · India

Apr 2015 – May 2018 · 3 yrs 1 mo

Sep 2014 – Apr 2015 · 7 mos

• Development of AIP for AMBA AXI-4 LITE Master:
• Given the specification of AMBA AXI-4 LITE protocol, creating a AIP
• Coded some of the planned rules as in AIP using System Verilog Assertions(SVA)
• Verified the AIP using onespin 360, formal verification tool.
• Test-bench Development (System Verilog):
• Architected class based verification environment for extended Memory Controller and FIFO including Functional coverage and Code coverage.
• Architected class based verification environment for Serial to Parallel Converter including Code Coverage.
• RTL Design:
• Implementation of design AMBA AHB- Lite protocol (Master – in progress)
• Design and Synthesis of FIFO, Stack, Edge Marker, Serial To Parallel Converter, Extended Memory Controller And Loadable Up-Down Counter.

Nov 2012 – Dec 2012 · 1 mo · Greater Chennai Area

• Designed and implemented an circuit for controlling the doors electronically.

Jun 2012 – Jul 2012 · 1 mo · Greater Chennai Area

Dec 2011 – Jan 2012 · 1 mo · Greater Chennai Area