Ayushi M.

Software Engineer

Bengaluru, Karnataka, India6 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL Design and Verification methodologies.
Proven track record in Analog Mixed Signal Verification.
Strong leadership and management skills in engineering teams.

Stackforce AI infers this person is a Silicon Design Engineer with expertise in Hardware Verification and Analog Mixed Signal technologies.

Contact

Skills

Core Skills

Analog Mixed Signal VerificationFormal VerificationRtl DebugUvmFunctional VerificationIpxact Register Mapping

Other Skills

functional coverageRegister modelAXI/AHB bus protocolDDR5 verificationLPDDR5Hardware VerificationRTL DesignCode CoverageRTL VerificationVerilogSystemVerilogUniversal Verification Methodology (UVM)Application-Specific Integrated Circuits (ASIC)ARM ArchitectureField-Programmable Gate Arrays (FPGA)

Experience

6 yrs 4 mos

Total Experience

2 yrs 1 mo

Average Tenure

4 yrs 9 mos

Current Experience

Amd

3 roles

Senior Silicon Design Engineer

Promoted

Jul 2025 – Present · 11 mos

Silicon Design Engineer 2

Promoted

May 2023 – Jun 2025 · 2 yrs 1 mo

Analog Mixed signal verificationFormal Verification

Silicon Design Engineer 1

Jul 2021 – Apr 2023 · 1 yr 9 mos

RTL DebugUVM

Arm

Verification Intern

Jan 2021 – Jun 2021 · 5 mos · Bengaluru, Karnataka, India · Remote

Enhancement on code coverage collection with MARKERS and Coarse Grain Test Scenario Intent Mapping for AI based intelligent coverage collection.

functional coverageFunctional Verification

Eunoia. magazine

Editor

Aug 2020 – Jul 2021 · 11 mos

Stmicroelectronics

Design Intern

Jan 2020 – May 2020 · 4 mos · Noida, Uttar Pradesh, India · On-site

Automation in managing Register Data in the Design with Magillem tool and capturing the same in industry grade IP-XACT.

Register modelIPXACT Register Mapping

Nit kurukshetra

Internship Coordinator

Apr 2019 – Dec 2019 · 8 mos · kurukshetra

Education

National Institute of Technology, Kurukshetra, Haryana

Bachelor of Technology - BTech

Jan 2017 – Jan 2021

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