Bandaru Venkatesh

Software Engineer

Bengaluru, Karnataka, India8 yrs 1 mo experience

Key Highlights

Expert in Formal Verification for complex hardware designs.
Presented at Intel FV Global Summit on deep-bound bugs.
Silicon perfectionist ensuring architectural correctness.

Stackforce AI infers this person is a Formal Verification Engineer specializing in complex hardware design verification.

Contact

Skills

Core Skills

Formal VerificationComputer ArchitectureVector ProcessingCache VerificationData Path Verification

Other Skills

Model CheckingASIC VerificationSystem VerilogData StructuresObject-Oriented Programming (OOP)FPGAPERLVerilogC++MatlabMicrosoft OfficeCvivadoQuesta SimC (Programming Language)

About

I am a Formal Verification Engineer and a silicon perfectionist, specializing in mathematical methods to ensure architectural correctness in complex hardware designs. My focus is on tackling deep-bound bugs that are undetectable by traditional simulation. I leverage Formal Verification techniques to build confidence in the silicon that powers devices like the Google Pixel. Core Technical Expertise: Formal Verification of Caches and out-of-order cores Writing assertion-based verification testbenches and formal models Expertise in E2E checks, formal abstractions, and convergence Previously, I contributed to critical IP verification at Arm (Vector Processing Unit) and Intel(Caches and schedulers ). I believe verification is about guaranteeing design behavior, not just debugging RTL. I even presented my approach in a paper titled "Uncovering deep bound bugs: FV with a Cape" at the Cadence Club Formal India and Intel FV Global Summit.

Experience

8 yrs 1 mo

Total Experience

1 yr 10 mos

Average Tenure

7 mos

Current Experience

Google

Formal Verification Engineer

Oct 2025 – Present · 7 mos · Bengaluru, Karnataka, India · Hybrid

Formal VerificationComputer Architecture

Arm

Senior Formal Verification Engineer

Sep 2023 – Sep 2025 · 2 yrs · Cambridge · Hybrid

ARM CPU Formal team. Worked on formal verification of Vector Processing unit

Formal VerificationVector Processing

Intel corporation

Senior Formal Verification Engineer

Dec 2020 – Aug 2023 · 2 yrs 8 mos · Bangalore Urban, Karnataka, India

Worked on verifying Intel IP's using Formal Methods. I have worked on formal verification of cache controllers , schedulers and cross bars designs.

Model CheckingFormal VerificationCache Verification

Synopsys inc

Application Engineer I

Jun 2018 – Dec 2020 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Formal Verification Team.
Worked with Customers addressing queries related to VC formal tool, formal methodology,
debugging and Convergence . Have worked on different formal methods like
Property Verification, Data Path Verification , Formal Coverage and VC Formal Sign-off flow with
various customers. Worked as Product validation for various features of VC Formal and Hector tools. Worked on verification of data path designs using HECTOR and a very good knowledge on floating point arithmetic.

Model CheckingFormal VerificationData Path Verification

Samsung electronics

Software Engineering Intern

Jan 2018 – May 2018 · 4 mos · Noida Area, India

Developed a chatbot based android application for scheduling the meetings to the user.

Mentor graphics

Intern

May 2017 – Jul 2017 · 2 mos · Noida Area, India

Underwent hands on training in verification of electronic design and systems using system verilog with QUESTASIM 10.5 tool and concepts of UVM methodology for design verification. Completed a
PROJECT on - ASIC Verification of LC3 Microcontroller(unpipelined) using concepts of System Verilog.