Anindya Nandi

CTO

Bengaluru, Karnataka, India23 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Extensive experience in hardware engineering leadership.
Expertise in power management and formal verification.
Proven track record in SOC design and verification.

Stackforce AI infers this person is a Hardware Engineering Leader with expertise in SOC design and verification.

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Skills

Core Skills

Processor Core Design & VerificationPower Management VerificationFormal Verification

Other Skills

FullChip Stimulus & DebugGate Level SimulationTop level verification planFunctionally verified IPsDFT DV activitiesSOC level formal verificationFormal verification flowsATPGVerification IP developmentDesign verification methodologiesSoCSimulationFunctional VerificationSystemVerilogEDA

Experience

23 yrs 1 mo

Total Experience

5 yrs 9 mos

Average Tenure

10 yrs 10 mos

Current Experience

Nvidia

4 roles

Sr. Director, Hardware Engineering

Promoted

Mar 2026 – Present · 1 mo

Director, Hardware Engineering

Promoted

Mar 2019 – Feb 2026 · 6 yrs 11 mos

Senior Manager, Hardware Engineering

Mar 2016 – Feb 2019 · 2 yrs 11 mos

Manager, Hardware Engineering

Mar 2015 – Feb 2016 · 11 mos

Amd

4 roles

Principal Member of Technical Staff

Feb 2015 – Mar 2015 · 1 mo

Manager / SMTS Design Engineering

Promoted

Jul 2012 – Jan 2015 · 2 yrs 6 mos

✪ Processor Core Design & Verification
✪ Led multiple functions for two SOCs in parallel and managed associated teams
KV SOC Power Management Verification
Console SOC Power Management Verification
KV SOC FullChip Stimulus & Debug
Console SOC Gate Level Simulation
Console SOC FullChip Stimulus & Debug
✪ Hands-on execution of several complex & time-critical tasks including
Verification of several customer use cases (Secure Resume, Early NB Pstate) in by devising multiple environmental tweaks
Top level verification plan for Connected Standby and technical guidance on execution of the plan
Analyzed & root-caused design behavior leading to several design bugs

Processor Core Design & VerificationPower Management VerificationFullChip Stimulus & DebugGate Level SimulationTop level verification plan

Member of Technical Staff / Section Manager Design Engineering

Apr 2010 – Jun 2012 · 2 yrs 2 mos

✪ Played key role in bring-up of a game-console SOC.
✪ Simultaneously led power management verification activities for a client SOC and a console SOC
✪ Played key role in verification of TN1, TN2, ORC0 enabling few back-to-back successful quality tape-outs in a short period.
✪ Led power management verification activities for a mainstream server. Simultaneously provided consultancy to the power management verification team for a mainstream client.
✪ Led the power management verification center of excellence.

Senior Design Engineer

Jan 2009 – Apr 2010 · 1 yr 3 mos

✪ Led power management verification of a server SOC

Texas instruments

Lead Engineer

Jun 2008 – Jan 2009 · 7 mos

✪ Functionally verified few IPs in the SoC context
✪ Drove DFT DV activities
✪ Led SOC level formal verification activities

Power Management Verification

Interra systems

4 roles

Project Leader

Jun 2007 – Jun 2008 · 1 yr

✪ Functionally verified few IPs in DSP SOCs
✪ Developed and deployed formal verification flows for the first time in DSPS designs in TI-H
✪ Led DFT DV activities

Functionally verified IPsDFT DV activitiesSOC level formal verificationFormal Verification

Lead Engineer

Jan 2006 – May 2007 · 1 yr 4 mos

✪ Formal Verification based solution for path delay fault ATPG
✪ Formal Verification of multiple functional & DFT IPs
✪ Formal Verification of SOC logic
✪ Led Interra’s Formal Verification team at TI India

Functionally verified IPsFormal verification flowsDFT DV activitiesFormal Verification

Senior Software Engineer

Jun 2004 – Dec 2005 · 1 yr 6 mos

✪ PCI-XP Verification IP development
✪ Research works on design verification methodologies
✪ Started & built Interra's Formal Verification group at the client (TI India) site.

Formal VerificationATPG