Neeraj Kothari

Software Engineer

Bengaluru, Karnataka, India10 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC Design Verification with extensive experience.
Proven track record in mentoring and training engineers.
Awarded SPOT award for outstanding contributions.

Stackforce AI infers this person is a Semiconductor Verification Engineer with strong expertise in ASIC design.

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Skills

Core Skills

Functional VerificationDesign Verification Testing

Other Skills

Universal Verification Methodology (UVM)DebuggingVerilogSystem VerilogI2C protocolSequential Equivalence CheckingMESI protocolComputer ArchitectureCMatlabMicrosoft OfficeLinuxPerlxilinxFormal Verification

Experience

10 yrs 7 mos

Total Experience

3 yrs 6 mos

Average Tenure

9 yrs 10 mos

Current Experience

Nvidia

ASIC Design Verification Engineer

Jun 2016 – Present · 9 yrs 10 mos · Bengaluru Area, India

Midcore Verification:
Owning and developing Midcore testbench.
Work closely with designers and architects to understand features to be implemented and verified.
Develop verification plan, run and maintain regressions, debug and analyze test results, and report design bugs.
Mentor engineers on the team, manage and track verification development schedules.
DGX-FPGA (System Management router):
Understanding of I2C protocol and DGX-FPGA design.
Critical member of DGX-FPGA verif team, responsible for verification of multiple blocks and features of FPGA.
Trained engineers both off-site and on-site.
Received SPOT award.
Post-silicon Validation:
Wrote exhaustive self-checking test cases.
Debug using GDB and report.
CPU core Verification:
Strong knowledge of CPU core micro-architecture.
Familiar with the cosimulation between the RTL and the micro-architectural C model using System Verilog models.
Worked on core_mix framework which enables the inter-mixability of random/directed tests.
Developed test scenarios to ensure maximum coverage of CPU core features.
Wrote benchmarks for testing cache performance.
Responsible for regression management and debug, functional and code coverage analysis.
Strong debugging and logic skills.
Mentored engineers.

Universal Verification Methodology (UVM)Functional VerificationDebuggingVerilogSystem VerilogDesign Verification Testing

Bits pilani, hyderabad campus

Teaching Assistant

Jan 2016 – May 2016 · 4 mos · Hyderabad Area, India

Teaching assistant at Computer architecture course at Electronics Department
Helped students in the lab problems, cleared their doubts.
Helped in making course assignments and creating difficult problem for the Comp Arch lectures.

Nvidia graphics pvt. ltd.

Intern

Jul 2015 – Dec 2015 · 5 mos · Bengaluru Area, India

Comprehensive clock gating verification by employing Sequential Equivalence Checking(SEC). Checked the sanity of the features and hence verified all the aspects of the design with/without the power optimization enablement.
Worked on the coherency block which maintains the coherency at outer most level of cache hierarchy. Understood the data flow and transactions between the CPU caches as a result of commands issued by clients of coherency block.
Understood the MESI protocol.

Madras atomic power station

Summer Intern

May 2014 – Jul 2014 · 2 mos · India

Design of wirelessly transmitting temperature sensor -
This project involved resistance temperature detectors (RTD) employed to measure the difference in resistance, due to difference in temperature, at places which are difficult to reach or are not accessible to humans at all. Such places include sea water influx, boiler, turbine, radioactive places, etc. The temperature data was sent by the Radio frequency module over a long range and received by a receiver module. This data is then sent to the microprocessor which converts it into temperature and shown on the LCD monitor.