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Brajesh Agrawal

CEO

Hyderabad, Telangana, India19 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in VLSI design and ASIC development.
  • Proficient in multiple hardware description languages.
  • Strong background in debugging and logic synthesis.
Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in hardware development.

Contact

LinkedIn

Skills

Other Skills

ASICAlgorithmsCC++CVSData StructuresDebuggingEDAGNU DebuggerLogic SynthesisRTL designSoCSystemVerilogVHDLVLSI

Experience

19 yrs 9 mos
Total Experience
9 yrs 11 mos
Average Tenure
14 yrs
Current Experience

Mentor graphics

3 roles

LMCS

Promoted

Aug 2018 – Present · 7 yrs 10 mos

Member of Consulting Staff

Aug 2014 – Jul 2018 · 3 yrs 11 mos

Lead Member of Technical Staff

Apr 2012 – Jul 2014 · 2 yrs 3 mos

Atrenta

Lead Engineer

Jul 2006 – May 2012 · 5 yrs 10 mos

Education

Indian Institute of Technology, Bombay

Master of Technology (M.Tech.) — VLSI designing

Jan 2004 – Jan 2006

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