D

Deepa Mariam Thomas

Product Manager

India14 yrs 7 mos experience
Highly Stable

Key Highlights

  • 14 years of experience in VLSI front-end design.
  • Expert in Verilog and SystemVerilog methodologies.
  • Certified in Xilinx FPGA design and synthesis.
Stackforce AI infers this person is a VLSI design expert with a focus on high-performance computing.

Contact

Skills

Core Skills

VlsiRtl Design

Other Skills

Micro architectureRTL CodingMulti Clock Domain Synchronization SchemesPower AnalysisFunctional Coverage AnalysisLintingSynthesis environmentStrategyMarket ResearchBusiness StrategyAnalytical R&DVerilogSystemVerilogFunctional VerificationVHDL

About

14 years experience in VLSI front end Design domain. Responsible for end to end design delivery for high performance CPU, GPU and MCU processor subsystems, Post Silicon and Methodology enhancements fostering AI in design checks Proficient in Verilog Hardware Description Language Knowledge about PCI Express Gen3 Link Equalization Procedure, MIPI-MPHY, APB and SPI protocols. Experience in Micro-architecture and block design Implemented various Multi-Clock Domain Synchronization schemes Experience in Static and Dynamic power Analysis Familiar with Lint and Synthesis environment Have undergone training in System Verilog, UVM methodology, Code coverage and Functional Coverage analysis Familiar with Perl scripting Certified in Xilinx FPGA design and synthesis

Experience

14 yrs 7 mos
Total Experience
6 yrs 11 mos
Average Tenure
9 mos
Current Experience

Arm

Solutions Engineering Staff Design

Sep 2025Present · 9 mos · Hybrid

Mediatek

4 roles

Senior Technical Manager

Oct 2022Oct 2025 · 3 yrs

Senior Staff Engineer

Promoted

Jan 2019Oct 2022 · 3 yrs 9 mos

Staff Engineer Design

Dec 2018Oct 2019 · 10 mos

Micro architectureRTL CodingMulti Clock Domain Synchronization SchemesPower AnalysisFunctional Coverage AnalysisLinting+3

Senior Engineer

Feb 2018Dec 2018 · 10 mos

Wipro technologies

Design Engineer

Jul 2011Oct 2017 · 6 yrs 3 mos · Kochi,Kerala

  • Design Engineer at Wipro Technologies
  • Experience in Micro architecture and design document preparation
  • RTL Coding and block design
  • Multi Clock Domain Synchronization Schemes
  • Power Anlaysis using Synopsys Prime Time tool
  • Functional and Code Coverage Analysis
  • Linting and Synthesis environment

Education

Indian Institute of Science (IISc)

Technology Management

Jan 2015Jan 2017

Rajagiri School of Engineering and Technology

Bachelor's Degree — Electronics and Communication Engineering

Jan 2007Jan 2011

Rajagiri Public School, Kalamassery

High School — COMPUTER SCIENCE

Jan 2002Jan 2007

Stackforce found 100+ more professionals with Vlsi & Rtl Design

Explore similar profiles based on matching skills and experience