Deepak Sherlekar

CEO

Cupertino, California, United States39 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI and ASIC design methodologies.
Extensive experience in R&D for semiconductor technologies.
Proven leadership as a Synopsys Fellow.

Stackforce AI infers this person is a semiconductor design expert with extensive experience in VLSI and ASIC technologies.

Contact

Skills

Core Skills

VlsiAsic

Other Skills

AlgorithmsVerilogMicroprocessorsEDASemiconductorsStatic Timing AnalysisDebuggingRTL designEmbedded SystemsICPhysical DesignR&DFPGASoCLow-power Design

Experience

39 yrs

Total Experience

7 yrs 9 mos

Average Tenure

15 yrs 9 mos

Current Experience

Synopsys inc

4 roles

Synopsys Fellow

Promoted

Oct 2020 – Present · 5 yrs 8 mos

VLSIAlgorithmsVerilogMicroprocessorsEDAASIC+15

Synopsys Scientist

Promoted

Oct 2017 – Oct 2020 · 3 yrs

Principal Engineer

Promoted

Sep 2013 – Oct 2017 · 4 yrs 1 mo

Senior Staff Engineer

Sep 2010 – Sep 2013 · 3 yrs

Virage logic corporation

Distinguished Member of Tech Staff

May 2002 – Sep 2010 · 8 yrs 4 mos

In-chip systems

Director, R&D

Jun 1997 – May 2002 · 4 yrs 11 mos

Ibm

Senior Engineer

Jan 1991 – Jan 1997 · 6 yrs · East Fishkill, NY, and Almaden, CA

University of michigan

Assistant Professor

Jan 1987 – Jan 1991 · 4 yrs · Ann Arbor

Education

University of Maryland

Ph.D. — Computer Science

Jan 1982 – Jan 1987

Indian Institute of Technology, Kanpur

M. Tech. — Computer Science

Jan 1979 – Jan 1981

GS Institute of Technology and Science

Bachelor of Engineering — Electronics Engineering

Jan 1974 – Jan 1979

Stackforce found 100+ more professionals with Vlsi & Asic

Explore similar profiles based on matching skills and experience

Rajendra Prasad

R&D Engineering Director

at Synopsys Inc

Mountain View, United States27 yrs 2 mos exp

ManagementMachine LearningLeadershipCustomer EngagementPeople Management

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp

Physical DesignMicroarchitecture

Prakash Mishra (प्रकाश मिश्रा)

Staff Engineer

at Synopsys Inc

Hyderabad, India7 yrs 11 mos exp

Analog Circuit DesignLow-power Design

Shubham Yadav

Senior Design Engineer

at Synopsys Inc

Bengaluru, India4 yrs 2 mos exp

Standard Cell Layout DesignPhysical DesignLayout Design

Khullar, Navneet

Vice President of Engineering

at Synopsys Inc

Sunnyvale, United States27 yrs 10 mos exp

Ajitesh Mishra

Senior Engineer

at Sandisk

Bengaluru, India7 yrs exp

Application-Specific Integrated Circuits (ASIC)Hardware EngineeringFunctional VerificationSAPDevOps

Akshay Kinake

Staff Signoff Application Engineer

at Synopsys Inc

Bengaluru, India3 yrs 11 mos exp

Full Chip timing signoffSMC 3DIC STATiming ClosurePerformance Optimization

Lovleen Arora

Principal Engineer, NAND SubSystem Device Engineering

at Western Digital

Bengaluru, India9 yrs exp

NAND Flash MemorySystem DesignProduct Development