Jan 2022 – Mar 2025 · 3 yrs 2 mos · Bangalore Urban, Karnataka, India

• Worked on DDR5/LPDDR5 Memory PHY development in TSMC-3nm
• ◦ Designed a high speed level shifter in Tx path for datarates from 1.6Gbps to 9.6Gbps. Actively interacted with the layout designer to improve the EMIR and self heat results.
• ◦ Ported a duty cycle adjuster circuit from TSMC-5nm to TSMC-3nm and performed various simulations to ensure that the specifications are met.
• ◦ Ported a constant gm circuit from TSMC-5nm to TSMC-3nm and made some sizing changes to improve the DC operating points.
• ◦ Participated in .lib generation of various macros using nanotime.
• Worked on GDDR6 Memory PHY development in TSMC-5nm
• ◦ Designed a strobe clock tree for sending 1GHz clock to all DQ lanes.
• ◦ Developed a python code to detect the floating and incorrect pode gate connections to avoid leakage.
• ◦ Performed a study on FMC and enabled the team for running FMC.

Jul 2019 – Dec 2021 · 2 yrs 5 mos · Bengaluru, Karnataka, India

• 32Gbps multiprotocol SerDes PHY (TSMC 7nm).
• I worked majorly in Rx and clocking circuits