R

Rajnish Kashyap

CTO

Noida, Uttar Pradesh, India8 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in Digital VLSI Design and Static Timing Analysis.
  • Strong background in semiconductor industry engineering.
  • Master's degree in VLSI System Design from a top institution.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and digital circuit design.

Contact

Skills

Core Skills

Digital Vlsi DesignStatic Timing Analysis

Other Skills

Digital Circuit DesignApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Field-Programmable Gate Arrays (FPGA)Analog Circuit DesignCC++Microsoft PowerPointVHDLVerilogRTL DesignFormal VerificationCustom DesignMixed-Signal IC DesignSystem Verilog

About

Experienced Component Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Digital VLSI Design, STA and Digital Circuit Design. Strong engineering professional with a Master's degree focused in VLSI SYSTEM DESIGN from National Institute of Technology Warangal.

Experience

8 yrs 9 mos
Total Experience
7 yrs 7 mos
Average Tenure
1 yr 2 mos
Current Experience

Qualcomm

Senior Lead Engineer

Feb 2025Present · 1 yr 2 mos

Intel corporation

2 roles

Component Design Engineer

Jul 2018Feb 2025 · 6 yrs 7 mos

Digital VLSI DesignStatic Timing AnalysisDigital Circuit Design

Digital Design Intern

Jun 2017Jun 2018 · 1 yr

Education

National Institute of Technology Warangal

Master's degree — VLSI SYSTEM DESIGN

UIT DEHRADUN

Bachelor's degree — Electronics and Communications Engineering

Stackforce found 100+ more professionals with Digital Vlsi Design & Static Timing Analysis

Explore similar profiles based on matching skills and experience