Pankaj Dhingra

CEO

Delhi, India6 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in VLSI Design and Mixed-Signal IC Design.
  • Proficient in RTL Coding and Logic Synthesis.
  • Strong background in Analog Circuit Design and Low-power Design.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor technologies.

Contact

LinkedIn

Skills

Other Skills

Altera QuartusAnalog Circuit DesignCCMOSCMOS Analog DesignCadence VirtuosoCommunicationDigital Circuit DesignElectronicsGenusHydrophonesInnovusLogic SynthesisLow-power DesignMixed-Signal IC Design

Experience

6 yrs 10 mos
Total Experience
4 yrs 9 mos
Average Tenure
2 yrs 1 mo
Current Experience

Cadence design systems

Lead Application Engineer

Apr 2024 – Present · 2 yrs 1 mo · Noida, Uttar Pradesh, India · On-site

Texas instruments

Digital Engineer

Jul 2019 – Apr 2024 · 4 yrs 9 mos · Greater Bengaluru Area

Education

Indian Institute of Technology, Bombay

Master of Technology (M.Tech.) — Electronic Systems

Jan 2016 – Jan 2019

Stackforce found 100+ more professionals with Altera Quartus & Analog Circuit Design

Explore similar profiles based on matching skills and experience

Aditya Tapase

Aditya Tapase

Senior GPU Verification Engineer

at NVIDIA

Mumbai, India6 yrs 6 mos exp
VLSIVerification
Saikrishna Jampuram

Saikrishna Jampuram

Senior Engineer

at Qualcomm

Bengaluru, India12 yrs 4 mos exp
Digital IC DesignPhysical Design
Jigar Pankhania

Jigar Pankhania

Product Development Engineer

at Intel Corporation

Bengaluru, India7 yrs 9 mos exp
Digital Circuit DesignVery-Large-Scale Integration (VLSI)Physical DesignPerformance Verification
VR

Vijaya R.

SoC Design Engineer

at Intel Tech. India Private Limited,Bangalore

Bengaluru, India16 yrs 10 mos exp
ASIC DesignDesign EngineeringIC DesignMixed Signal DesignPDN Analysis
sarveshwar kumar

sarveshwar kumar

Senior Engineer

at Arm

Bangalore Rural, India10 yrs 11 mos exp
Alok Jadhav

Alok Jadhav

Senior Design Verification Engineer

at Intel Corporation

Bengaluru, India11 yrs 5 mos exp
ASICFunctional Verification
SHANTANU JAWALE

SHANTANU JAWALE

Member of Technical Staff

at AMD

Bengaluru, India11 yrs 2 mos exp
Liraz Azriel

Liraz Azriel

Post Silicon Validation Engineer

at Intel Corporation

Israel20 yrs 9 mos exp
Silicon ValidationAnalog Signal ProcessingHardware Design