Dildar Hussain

Product Engineer

Bengaluru, Karnataka, India20 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in Physical Design across multiple technology nodes.
Proven track record in achieving optimal PPA metrics.
Hands-on experience with leading EDA tools.

Stackforce AI infers this person is a Physical Design Engineer specializing in ASIC and VLSI technologies.

Contact

Skills

Core Skills

Physical DesignSignoff Closure

Other Skills

Team BuildingFloorplan PartitionLeadershipFloorplanningplace & RouteSTAPhysical VerificationLow-power DesignStatic Timing AnalysisPower PlanningClock Tree SynthesisExtractionPower and Signal Integrity AnalysisOptimizationDRC

About

o Expertise in all aspect of Physical design including ”Synthesis, partitioning, floor planning, Power Planning, Place and Route, timing budgeting, clock tree synthesis, extraction, timing closure, power and signal Integrity analysis and optimization and Physical Verification”. o Hands on implementation and signoff closure for chip level, IP level and Block level across various technology nodes from 90nm to N3E. o Executed complex designs like GPU, Multimedia, DDRSS, Wireless Modem SS and MSIP and delivered optimal PPA metrics. o Hands on EDA Tools:  Synopsys (ICCII, Fusion compile, PrimeTime, PrimeTime-SI , Star-RCXT, DesignCompiler, Formality).  Cadence ( SOC-Encounter, Innovus, Conformal).  Mentor Graphics (Calibre).

Experience

20 yrs 3 mos

Total Experience

3 yrs

Average Tenure

2 yrs 1 mo

Current Experience

Google

Physical Design and Implementation Engineer

May 2024 – Present · 2 yrs 1 mo · Bangalore

Qualcomm

4 roles

Engineer, Sr Staff/Manager

Promoted

Feb 2021 – Apr 2024 · 3 yrs 2 mos · On-site

Leading and executing complex sub-system design cores for PD and Signoff closure in cutting edge tech nodes N3E and N4 and targeting to achieve best in class PPA.

Team BuildingFloorplan PartitionLeadershipFloorplanningplace & RouteSTA+2

Engineer, Sr Staff

Nov 2020 – Feb 2021 · 3 mos · On-site

Responsible to lead and execute physical Design including signoff closure for RFA designs - WMSS (wireless modem subsystem) - PD implementation for sub6 and mm-Wave design architectures across multiple projects.

Place & RoutePhysical VerificationLow-power DesignStatic Timing AnalysisPhysical DesignSignoff Closure

Staff Engineer

May 2017 – Nov 2020 · 3 yrs 6 mos · On-site

Worked on PPA for Modem sub system.
Responsible to lead and execute physical Design including signoff closure (STA/PDN/PV/FV/CLP) for DDR sub systems for multiple projects for Mobile and compute application SOCs.

Physical VerificationSTALow-power DesignPhysical DesignSignoff Closure

Lead Engineer, Sr

Aug 2014 – Apr 2017 · 2 yrs 8 mos · On-site

Responsible to lead and execute physical Design including signoff closure of Multimedia Camera sub subsystem design.
Worked on timing closure (STA) for Perf IHM and power IHM for CPU designs.
Responsible for hierarchical PNR implementation and signoff closure of A53 GOLD MHM targeted for Fmax and Area optimization.

STAPhysical DesignSignoff Closure

Broadcom

Engineer Sr. Staff

Oct 2013 – Aug 2014 · 10 mos · Bangalore

Renesas mobile corporation

Sr.Design Engineer ASIC

Jul 2011 – Sep 2013 · 2 yrs 2 mos · Bangalore, India

Working for Wireless Modem Integration team "WM MSOC Modem Integration"
Responsibilities include complete Backend PNR flow from Netlist to GDS2 for a Wireless Modem.

Adventura technologies

AMS Design Engineer II

Jan 2011 – Jul 2011 · 6 mos · Bangalore

Worked on Digital Block Place & Route for a mixed signal IP,

Stmicroelectronics

Technical Lead

Jun 2007 – Jan 2011 · 3 yrs 7 mos · Noida Area, India

Worked for Physical Design Team of CCI at ST Microelectronics
My Responsibilities include complete ASIC Backend Flow from RTL to GDS2 and Subsystem level Syntheis and DFT.