Gnan Raj Talla — Product Engineer
Physical Design Engineer with 5+ years of experience in Block level implementation from advanced tech nodes. Executed various engagements on PPA improvements, fmax push, timing and DRC closure. Strong expertise in physical design concepts - Placement, CTS, Routing, Secondary PG connection and ECO implementation. Excellent Collaboration with customers in driving them towards design closure.
Stackforce AI infers this person is a Physical Design Engineer specializing in VLSI and ASIC technologies.
Location: Hyderabad, Telangana, India
Experience: 7 yrs 7 mos
Skills
- Physical Design
- Asic
- Timing Closure
- Vlsi
Career Highlights
- 5+ years in physical design engineering.
- Expertise in timing closure and DRC.
- Strong collaboration skills with clients.
Work Experience
Intel Corporation
Physical Design Methodology Engineer (1 yr 11 mos)
Synopsys Inc
Senior Applications Engineer 1 (3 yrs)
Application Engineer II (2 yrs 2 mos)
(Intern) Technical Engineering (10 mos)
Education
M.Tech at Motilal Nehru National Institute Of Technology
Engineer's Degree at Osmania University
Associate’s Degree at Sri Chaitanya Junior Kalasala
High School at Saint Joseph High School
