Apr 2024 – Jun 2025 · 1 yr 2 mos · Hyderabad · On-site

• Worked on PnR closure for a 3nm subsystem container project, including voltage region creation, TMAC insertions, and RDL routing on critical nets to meet design and performance requirements.
• Responsible for block-level floor planning, including memory and pin placement, ensuring optimal alignment with the full-chip floorplan for improved routing efficiency and performance.
• Collaborating with cross-functional teams to resolve netlist, UPF, and IP-related issues, ensuring a seamless design flow and efficient signoff closure at the full-chip level.
• Managing full-chip requirements, including custom cell additions during ECOs, last-minute port modifications, and manual antenna fixes, ensuring design integrity and smooth signoff closure.
• Manually routing critical nets in RDL while ensuring DRC, LVS, and antenna rule compliance, with a strong focus on design robustness and manufacturability.
• Leading the Library Preparation Team and managing three projects, overseeing library development, validation, and integration to ensure seamless design execution across multiple technology nodes.

Jul 2023 – Apr 2024 · 9 mos

• Worked on the TSMC N4 Subsystem Container Project, focusing on PnR closure, voltage region creation, TMAC insertions, and RDL routing of critical nets as per design requirements. The subsystem container comprises approximately 155 blocks and 20 macros, with four voltage domains, including Always-On and On-Off domains. Key challenges involved routing multi-fanout nets within the correct voltage domain while ensuring DRC, LVS, and antenna rule compliance, with a strong emphasis on manual RDL routing and design integrity.
• Worked on two blocks in a TSMC N5 technology node project—one with 1 million instances and 40 RAMs as an on-off block, and another with 600K instances as a multi-voltage block. Responsibilities included performing sanity checks, floor planning, and PnR implementation. Key challenges involved addressing congestion and timing issues, particularly in the on-off block, which had high pin-density cells and critical gate-to-register paths. In the multi-voltage block, ensured proper voltage region creation and strategic placement of region breaker cells to optimize power and signal integrity.
• Worked on Full-Chip Functional Closure Timing (FCT) for Design Rule Violations (DRV), noise, and glitch violation resolution in a TSMC N5 project, ensuring robust signal integrity and design reliability.
• Worked on a TSMC N6 technology node project, handling a complex on-off block with 1.5 million instances and 60 RAMs. Focused on optimizing design implementation, ensuring efficient power management, and meeting performance and timing requirements.

May 2020 – Jul 2023 · 3 yrs 2 mos

• Responsible for handling the design from Netlist to delivering the GDS II for multiple blocks in 6nm,5nm & 4nm

Nov 2019 – May 2020 · 6 mos

• Responsible for handling the design from Netlist to delivering the GDS II for multiple blocks in 180,130 and 90 nm

May 2019 – Oct 2019 · 5 mos · Hyderabad Area, India · On-site

• Trained on handling the design from Netlist to delivering the GDS II for multiple blocks in 90nm, 130nm,180nm

Nov 2015 – May 2016 · 6 mos · Vijayawada Area, India

• Responsible for the Production, Testing, Debugging and Maintenance of Embedded Systems.