HARISH DAMARLA

Product Manager

Bayan Lepas, Penang, Malaysia7 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Achieved 100% scan coverage in ATPG.
Successfully completed Buntzen ASIC turnkey project.
Extensive experience in DFT methodologies and tools.

Stackforce AI infers this person is a DFT Engineer specializing in ASIC VLSI design and testing methodologies.

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Skills

Core Skills

AtpgDftMbist

Other Skills

Automatic Test Pattern Generation (ATPG)DFT- CompilerTetraMaxTestMaxVcsScan InsertionSimulationsBISTTessentSupraFusion compilerScan coverageTest CoverageMemory TestSRAM

About

Skilled DFT Engineer, having both theoretical and practical knowledge on Boundary Scan, Scan Insertion, DRC Violation, Fixing of DRC's, Compression, OCC, and Stuck at and Transition ATPG, Simulation. MBIST insertion, generation of patterns and validation, SOE. Have the knowledge on Digital Design, fundamentals of Verilog and Tcl scripting.

Experience

7 yrs 4 mos

Total Experience

1 yr 10 mos

Average Tenure

2 yrs 5 mos

Current Experience

Ust

Associate III - VLSI

Jan 2024 – Present · 2 yrs 5 mos · Bayan Lepas, Penang, Malaysia · On-site

Working as a Service Provider Worker for AMD Malaysia.
Below are roles and responsibilities
Worked on Scan - ATPG Supra flow for block level
Worked on scan insertion using Synopsys - Fusion Compiler
Fixed Scan DRC’s during the scan insertion
Achieved 100% scan coverage
Worked on ATPG using Tessent - TestKompress tool
Fixed ATPG DRC’s during ATPG
Worked on generating patterns for Intest (EDT & Bypass)
Worked on generating patterns for Extest (EDT & Bypass)
Worked on notiming simulations on Synopsys - Verdi

Automatic Test Pattern Generation (ATPG)DFT- CompilerTetraMaxTestMaxVcsATPG+1

Ignitarium

Senior Engineer

Jul 2023 – Jan 2024 · 6 mos · Bengaluru, Karnataka, India

Worked on Buntzen ASIC turnkey project. Scan Insertion and fixing of scan DRCs. ATPG with UDR bit programming for enabling EXTEST logic.
Generated stuck at pattern .
Improved coverage with the help of IB and OB chains by doing EXTEST logic. Performed timing and no-timing simulations. Received award for the completion of the project.

Excelmax technologies

DFT Engineer

Oct 2019 – Jul 2023 · 3 yrs 9 mos · Bengaluru Area, India · On-site

Worked as a Product Development Engineer for INTEL Malaysia client. Handled multiple projects on different releases. Below are roles and responsibilities.
Worked on MBIST Insertion and Pattern Generation and Validation
Worked on Stop on Error (SOE)
Worked on Stop and Resume (SAR)
Worked on Functional Debug Mode (FDM)
Worked on Repair Validation
Worked on BISR Repair
Worked on Raster Validation
Worked on Simulations

BISTDFTMBIST

Semicon technolabs pvt. ltd.

DFT Engineer Trainee

Oct 2018 – Sep 2019 · 11 mos · Bengaluru, Karnataka, India

As a DFT trainee, I have a very good theory and as well as practical knowledge of DFT concepts like Boundary scan, Scan Insertion, DRC, Compression, OCC, ATPG and Simulation. Knowledge on Digital Design, Basic fundamentals of Verilog and TCL scripting. Experience with Cadence tools of genus legacy_ui, encounter test, NCsim

Ceyon

Software EngineerTrainee

Feb 2018 – Oct 2018 · 8 mos · Greater Hyderabad Area

Job Searching application- Developing a full application where I was assigned with Front end, Database and Backend of the application. To and flow actions from Jobseeker to Employer has been done. Data insertion, updating the data, deleting the data and retrieving the data from the database.