Harpreet Singh Budwal

Engineering Manager

Bengaluru, Karnataka, India12 yrs 10 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Expert in driving semiconductor innovation.
Proven track record in managing engineering teams.
Strong algorithmic expertise in advanced nodes.

Stackforce AI infers this person is a leader in the VLSI/EDA industry with a focus on advanced semiconductor design.

Contact

Skills

Core Skills

Physical DesignTechnical LeadershipP&r ToolResearch And DevelopmentRtl-to-gdsiiEda

Other Skills

PPA SolutionsAI ToolsML FrameworksPPA ImprovementCollaboration with FoundryCutting Edge TechnologiesCPU CoresP&RPython (Programming Language)RTL CodingVerilogECOStatic Timing AnalysisSignal IntegrityDesign Rule Checking (DRC)

About

Tech-savvy Engineering leader in 13th year of contributing to VLSI/EDA industry. Track record of managing large-scale customer engagements, architecting cutting edge workflow automation and PPA solutions, leading teams, and delivering innovative algorithms. I enjoy working on complex problems and solving them in collaboration with teams. Driving next-generation semiconductor innovation across advanced nodes through deep algorithmic expertise, strong customer alignment, and high-impact technical leadership

Experience

12 yrs 10 mos

Total Experience

6 yrs 5 mos

Average Tenure

9 yrs 11 mos

Current Experience

Synopsys inc

4 roles

Engineering Manager

Promoted

Jun 2024 – Present · 2 yrs

In this role, I'm leading strategic technical initiatives and managing an engineering team delivering critical physical design PPA solutions and CAD flows for advanced semiconductor nodes. Serving as the primary liaison between R&D development teams and tier-one customers, orchestrating complex multi-module enhancements and foundry certifications for enhanced PPA convergence. Leveraging AI tools and ML frameworks to drive productivity enhancements.

Physical DesignPPA SolutionsAI ToolsML FrameworksTechnical Leadership

Staff R&D Engineer

Feb 2023 – Jul 2024 · 1 yr 5 mos

In this role, I was responsible to Research, Architect, Develop, and Deploy differentiating technology in P&R tool to provide substantial PPA improvement on Advanced Nodes by work in close collaboration with Foundry with an additional responsibility of managing an passionate team.

P&R ToolPPA ImprovementCollaboration with FoundryResearch and Development

Senior II R&D Engineer

Jun 2019 – Feb 2023 · 3 yrs 8 mos

In this role, I was responsible to enhance PPA for P&R RTL-To-GDSII tool by deploying latest cutting edge technologies on CPU cores.

RTL-To-GDSIICutting Edge TechnologiesCPU CoresPhysical Design

Senior R&D Engineer

Jul 2016 – Jul 2019 · 3 yrs

In this role, I worked to enhance the P&R tool to further push the PPA for the CPU/GPU cores.

EDAPhysical DesignP&RResearch and Development

Intel corporation

Grpahics Engineer

Jul 2013 – Jun 2016 · 2 yrs 11 mos · Bangalore

In this role, my responsibility was to implement, validate, and deploy new feature in graphics processor. A highlight of my work was contributing key features to a recently released SOC, for which I receive my award and recognization.