Hemanth H N

Software Engineer

Bengaluru, Karnataka, India10 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in CPU power management logic design.
Proven track record in digital signal processing.
Led functional safety features in complex systems.

Stackforce AI infers this person is a Semiconductor Engineer specializing in Digital Design and Signal Processing.

Contact

Skills

Core Skills

Power ManagementDigital Logic DesignSystem On A Chip (soc)Digital Signal Processing

Other Skills

RTL CodingGate Level SimulationClock Domain CrossingUPFVHDLMatlabDigital CommunicationVLSI Logic DesignElectronicsVerilogCC++HTMLMS officeMS Excel

About

I'm an Engineer who believes in Einstein's quote "Imagination is more powerful than knowledge". I go deep in the topic where I work to get learnings which are highly valuable to my work. This gives me the good feeling of satisfaction. My passion lies in Digital Design & solving any problem in digital design 😍 Currently I'm solving the CPU power problems. Previously I have solved problems related to Digital Communication & Digital Signal Processing.

Experience

10 yrs 8 mos

Total Experience

5 yrs 4 mos

Average Tenure

7 yrs 2 mos

Current Experience

Intel corporation

2 roles

Logic Design Engineer - Processor Power Management; P-Core (both Client & Server)

Promoted

Jun 2020 – Present · 6 yrs · Bengaluru, Karnataka, India

Worked as logic design engineer
Worked on Processor Power Management unit which controls different power & reset flows of a performance-centric Processor.
Did debugs caught in validation and emulation.
Involved in Post-Si debugs & fixes.
Worked on CDC/RDC
Worked on Gate Level Simulation (GLS) and debugging
Interacted with Arch team and did TRs (Technical Readiness) for new & legacy features in Processor Power Management unit.
Have done VT-Lead role to lead a functional safety feature at Core level. Understood the feature at full SoC/Core level & making sure all the cluster's architects, designers and validators are aligned to product goal via weekly sync meeting.

RTL CodingDigital logic designPower ManagementGate Level SimulationClock Domain Crossing

SoC Design Engineer - UPF

Apr 2019 – Jun 2020 · 1 yr 2 mos · Bengaluru, Karnataka, India

Worked on the SoC UPF IEEE 1801 std.
Did UPF reviews and wrote upf for SoC subsystems

System on a Chip (SoC)UPFRTL Coding

Coreel technologies

2 roles

Senior System Design Engineer

May 2018 – Apr 2019 · 11 mos

Supported previously delivered Radar projects to customers
Worked on Video and Audio encoder and decoder chip.

RTL CodingDigital logic design

System Design Engineer

Sep 2015 – Apr 2018 · 2 yrs 7 mos

Worked on Logic Design & Digital Signal Processing in Radar/Sonar technology and Digital communication.
Worked on DBPSK/DQPSK digital modulation and demodulation and successfully implemented in hardware/FPGA using VHDL.
Wrote Matlab code for modeling the DBPSK/DQPSK communication algorithms and implmemted the same in FPGA.
Implmemted Costas loop algorithm to recover carrier to successfully demodulate the received signal in DQPSK with high SNR and got recognised for this work.
Worked on Radar/Sonar signal generator and Radar signal reciever.
Worked on ADC & DAC data converters.

RTL CodingDigital logic designDigital Signal ProcessingVHDL