Ipshita Datta

Product Engineer

Raleigh, North Carolina, United States5 yrs 3 mos experience

Key Highlights

Expert in ASIC Design Verification and digital hardware design.
Proficient in GPU-accelerated simulations for telecommunications.
Strong background in Python and MATLAB for system modeling.

Stackforce AI infers this person is a Telecommunications and Semiconductor specialist with expertise in ASIC Design and verification methodologies.

Contact

ipshita.datta@hsc.com LinkedIn

Skills

Core Skills

Asic Design VerificationDigital Hardware Design

Other Skills

ArduinoC (Programming Language)C++CUDADesign Rule Checking (DRC)Functional verification conceptsGenusLinuxMATLABMicrosoft WordPrinted Circuit Board (PCB) DesignPython (Programming Language)RTL analysisRoboticsShell Scripting

About

I am currently pursuing my master's in Computer Engineering with a strong interest in ASIC Design Verification, digital hardware design, and semiconductor technologies. I enjoy breaking down complex hardware concepts and validating designs through structured verification methodologies. My interests include SystemVerilog, Verilog, RTL analysis, simulation-based verification, and functional verification concepts. I am passionate about working on high-performance silicon and SoC designs.

Experience

5 yrs 3 mos

Total Experience

2 yrs 3 mos

Average Tenure

Current Experience

Hughes systique corporation (hsc)

3 roles

Research And Development Engineer

Apr 2025 – Jul 2025 · 3 mos

AI and Wireless Technology (Centre of Excellence Department)
● Designed GPU-accelerated physical-layer simulation pipelines using CUDA and NVIDIA Sionna to model OFDM transceiver chains and wireless channel behavior.
● Implemented hardware-realistic signal processing models to evaluate BER vs. SNR trade-offs under varying channel conditions.
● Developed real-time constellation visualization tools to analyze neural receiver performance during system-level validation.
● Built ML-assisted pipelines for 3D mmWave environment reconstruction supporting digital-twin modelling and wireless

Python (Programming Language)CUDAASIC Design VerificationDigital Hardware Design

Associate Engineer

Oct 2023 – Apr 2025 · 1 yr 6 mos

Modeled PHY-layer communication systems using GPU-accelerated simulations to evaluate receiver architectures.
Optimized simulation workflows using Python + CUDA, reducing execution latency for large-scale wireless experiments.
Implemented modular channel models to support hardware-aware performance evaluation.

MATLABDigital Hardware Design

Intern

Jan 2023 – Sep 2023 · 8 mos

Software Developer Engineer(intern)

Ieee ras ncu sb

3 roles

Mentor

Jul 2022 – May 2023 · 10 mos

Chairperson

Jun 2021 – Aug 2022 · 1 yr 2 mos

Vice Chair

Aug 2020 – Jun 2021 · 10 mos

Cadence design systems

Trainee Product Validation Engineer

May 2022 – Aug 2022 · 3 mos · Noida, Uttar Pradesh, India · Hybrid

Debugged RTL simulation failures using SystemVerilog and Verilog waveform analysis in silicon-validation environments.
Automated regression workflows using Python, Shell, and TCL to improve verification coverage and reduce manual debug time.
Collaborated with R&D teams to reproduce silicon-level issues and perform root-cause analysis on failing testbenches.

GenusShell ScriptingASIC Design Verification