Jagrut Jadhav

Product Engineer

Austin, Texas, United States3 yrs 2 mos experience

Highly StableAI Enabled

Key Highlights

Expert in hardware validation and automation strategies.
Pioneering AI integration for hardware failure analysis.
Proven track record in user-centric testing methodologies.

Stackforce AI infers this person is a Hardware Engineering specialist with a focus on validation and automation in tech products.

Contact

Skills

Core Skills

Verification And Validation (v&v)Test AutomationArtificial Intelligence (ai)Model Context Protocol (mcp)ValidationDebuggingComputer Hardware

Other Skills

Python (Programming Language)Shell ScriptingLinuxCXLQuality ControlAutomationVerilogCEmbedded SystemsComputer-Aided Design (CAD)ResearchElectrical EngineeringAnalog Circuit DesignC++Adobe Photoshop

About

As a Hardware System Quality DRI (Directly Responsible Individual) at Apple, I ensure the stability and reliability of next-generation Mac and Home products. My primary focus is bridging the gap between new silicon architectures and user experience. I design rigorous validation strategies that target critical system state transitions—Reboots, Sleep/Wake, and Hibernation—to uncover edge cases where hardware and software intersect. To achieve this at Apple's scale, I operate as a hybrid engineer. I architect the software ecosystem that powers our testing. I specialize in developing Python and Swift-based triage tools and am currently pioneering the integration of Generative AI and Model Context Protocols (MCPs) to automate complex failure analysis.

Experience

3 yrs 2 mos

Total Experience

3 yrs 2 mos

Average Tenure

3 yrs 2 mos

Current Experience

Apple

Tools and Automation Engineer

Mar 2023 – Present · 3 yrs 2 mos · United States · On-site

Hardware Validation & Strategy------------------->
Product DRI: Serve as the Directly Responsible Individual for upcoming Mac and Home products, leading quality validation from early prototype silicon through to mass production.
System State Stress Testing: Design and execute complex validation suites focused on critical power transitions (Sleep, Wake, Hibernate, Warm/Cold Boot). I engineer test logic specifically to stress hardware-firmware handshakes and catch panic/hang regressions.
User-Centric Edge Cases: Developed a "customer-first" testing methodology that translates real-world usage patterns into automated test vectors, identifying obscure hardware failures that standard synthetic benchmarks often miss.
HW/SW Correlation: Lead the root-cause analysis for complex stability issues, working directly with silicon and OS teams to determine if failures (panics, resets) are caused by physical hardware limitations or software logic.
AI & Intelligent Automation ------------------->
AI Integration & MCPs: Spearheading the adoption of AI in hardware triage by developing custom Model Context Protocols (MCPs). These AI agents autonomously parse massive datasets from test runs to correlate failures and suggest root causes, significantly reducing manual triage time.
Smart Triage Tools: Integrating LLM capabilities into legacy tools to provide "plain English" summaries of complex kernel logs and hardware register dumps for the wider engineering team.
Core Tooling & Development------------------->
Tool Ownership: Owner and primary developer of multiple Python and Swift-based applications used daily by the MSQ and Home teams for test execution and data visualization.
Infrastructure: Maintain and optimize the automation frameworks that orchestrate thousands of hours of stability testing across the lab.

Verification and Validation (V&V)Python (Programming Language)Test AutomationModel Context Protocol (MCP)Artificial Intelligence (AI)

Zt systems

Senior Validation Engineer

Jan 2023 – Mar 2023 · 2 mos · United States · On-site

Contributed to data-centers and server storage and validation, testing, and qualification of hardware and/or software
Worked on computer architecture, storage protocols, PCI Express, and networking to build hyper-scale and enterprise servers and storage systems
Experience with scripting using Python and Shell for developing and automating test cases.

Python (Programming Language)Shell ScriptingDebuggingValidationLinux

Intel corporation

System Validation Engineering Intern

Jan 2022 – Dec 2022 · 11 mos · Austin, Texas, United States

Experience with HSIO validation on Intel XEON processor. Good understanding of CXL and PCIe protocols.
Working with the Intel FPGA team in running the stress test for specific system configuration, debugging system issues, filling a token, and collaborating with the design team to resolve the errors.
Good understanding of Intel Xeon server architecture - multi core architecture and cache coherency architecture.
Designing an intelligent validation debug tool using Python, XML, and batch scripting to read and parse all the register values, automate tests, and output errors.
Executing different test cases for reset, register read and write, cache coherency, data comparison and time outs. Monitoring certain registers like program counters and status flag registers for change of values in certain time frame.

Python (Programming Language)CXLValidationComputer HardwareTest Automation

New jersey institute of technology

Front Desk Attendant

May 2021 – Jan 2022 · 8 mos · Newark, New Jersey, United States

Experience working on the front desk of the Residence Halls at NJIT and responsible for acting as the front line of security for the student communities housed within.
Being reliable and punctual to my job and taking quick decisions whenever required during my shifts.

Sq.m technologies

FPGA Engineering Intern

Jul 2020 – Dec 2020 · 5 mos · Mumbai, Maharashtra, India

Worked on designing top-level RTL logic on Xilinx Virtex Ultrascale (HTG930 board) for 6 core Helios soft-core processor with System Verilog.
Used Linux environment for python scripting and automating synthesis process with the TCL script.
Designing RTL structure, programming, synthesizing, simulating, and running HDL on Spartan 6 FPGA used in MRI scanner. Design Verification of the RTL designs before implementation using Waveforms on the simulator and using the chip scope tool after implementation on FPGA.
Worked on various protocols like UART, RS232, RS485, I2c (EEPROM) and MODBUS.

Indian institute of technology, bombay

EYIC project

Sep 2018 – Apr 2019 · 7 mos · Mumbai Area, India

Project -Defence Mechanism Using Image Processing
Worked on defence Semi automatic robot with multiple sensors and actuators
Used Image processing algorithms to detect enemy and interception of the target using a high power laser.
Won best demonstration award in IIT Bombay national competition and got recognition from DRDO.

Ramrao adik institute of technology

Firmware Intern

May 2017 – Jun 2017 · 1 mo · India

Developed an IOT based control system using STM32 microcontroller and ESP8266 to balance a ball at a user-defined distance on a beam using PID controller.
Acquired knowledge of scheduling tasks using Free-RTOS like TCP request, TCP respond, Actuator control and PID computation.