Mahima Bhatnagar

Product Manager

Bengaluru, Karnataka, India5 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Achieved 99% toggle coverage in validation.
Expert in pre-silicon verification methodologies.
Proficient in industry-standard simulation tools.

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in pre-silicon verification methodologies.

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Skills

Core Skills

Universal Verification Methodology (uvm)Pre-silicon ValidationTest Case Development

Other Skills

Synopsys VCSVerdiVenusVerification and Validation (V&V)Digital ElectronicsLinuxCadenceQuartus PrimeModel Sim

About

Executive Summary: A highly motivated and results-oriented Product Validation Engineer with four years of experience in the semiconductor industry. Proven ability to perform thorough pre-silicon verification using industry-standard methodologies and tools. Skilled in hardware languages (SystemVerilog), verification methodologies (UVM) and simulation tools (Synopsys VCS, Verdi, Venus). Key Highlights: - Working as a Product Validation Engineer II at Cadence Design Systems - Intel Technology India Pvt. Ltd: Performed pre-silicon validation on DFD domain for Trace fabric for Xeon servers, achieving 99% toggle coverage. Collaborated with various teams for efficient debugging and bug identification. - Wipro Technologies: Supported pre-silicon validation of Intel's client SoCs, specializing in the LNL variant. Developed and improved test cases and actively participated in debug. Technical Skills: - Hardware Languages: Verilog, SystemVerilog - Verification Methodology: UVM - Scripting Languages: Python - Simulation Tools: Synopsys VCS, Verdi, Venus, ModelSim - Operating Systems: Linux, Windows

Experience

5 yrs 5 mos

Total Experience

1 yr 7 mos

Average Tenure

3 yrs 3 mos

Current Experience

Cadence

Product Validation Engineer II

Mar 2025 – Present · 1 yr 1 mo · Greater Bengaluru Area · Hybrid

Intel corporation

Pre-Silicon Validation Engineer

Jan 2023 – Present · 3 yrs 3 mos · Bengaluru, Karnataka, India · Hybrid

Designation: Pre-Si Validation Engineer
Performed pre-silicon functional verification of Design for Debug (DFD) domain for Xeon server in the Trace and VISA fabric for the CWF project.
Perform verification of the DFD design, validating its functional characteristics and identifying potential design flaws or bugs.
Leveraged both simulation and emulation environments to comprehensively test the functionality and use cases of various DFD fabrics.
Collaborated effectively with SoC architects, RTL developers, and the post-silicon team to pinpoint and resolve RTL bugs, streamlining the debugging process.
Developed a comprehensive test case and corresponding verification tests aligned with project requirements.
Executed test case, validated test results, and performed debug activities using the Universal Verification Methodology (UVM).
Continuously learn from post-silicon validation results to improve the quality of pre-silicon verification processes, ensuring these improvements are incorporated into future product development.
Demonstrated expertise in industry-standard tools by proficiently using Synopsys VCS, Verdi, and Venus tools for simulation, debugging, and analysis tasks.

Universal Verification Methodology (UVM)Synopsys VCSVerdiVenusPre-Silicon Validation

Wipro

SOC verification engineer

Aug 2021 – Jan 2023 · 1 yr 5 mos · Bengaluru, Karnataka, India · Hybrid

Designation: Project Engineer | Pre-Si Validation of INTEL client SoCs
Worked as part of Audio and Context Engine (ACE) team on the PCH INTEL project.
Specialized in the LNL variant while providing support for MTLM variants.
Developed and maintained comprehensive test cases aligned with project requirements.
Enhanced the scalability of existing test cases for efficient reuse across multiple projects.
Debug the test cases and resolve critical issues

Universal Verification Methodology (UVM)Test Case DevelopmentPre-Silicon Validation