Jayadev E

Software Engineer

Bengaluru, Karnataka, India11 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Linux kernel and driver development.
Proven track record in embedded systems and performance optimization.
Strong leadership experience managing engineering teams.

Stackforce AI infers this person is a highly skilled Embedded Systems Engineer with extensive experience in firmware and driver development.

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Skills

Core Skills

Linux Kernel & Driver DevelopmentEmbedded Systems & Board Bring-upFirmware Development

Other Skills

ElectronicsEmbedded LinuxUser-kernel communication mechanismsIEEE 802.11 protocolsWLAN chipsetsFreeRTOSLow-level assemblyWorking ExperienceCode ReviewInternet of Things (IoT)Communication ProtocolsUniversal Asynchronous Receiver/Transmitter (UART)I2CSTM32Problem Solving

About

Passionate systems software engineer with a strong foundation in low-level programming, operating systems, and embedded development. I specialize in working close to the hardware — building, optimizing, and debugging system components that form the backbone of modern devices. With years of hands-on experience in Linux-based environments, I’ve worked on device drivers, board bring-up, kernel modules, and system-level performance tuning. I’m comfortable navigating complex problems across both kernel and user space, and I enjoy delivering efficient, reliable solutions at scale. Curious by nature and driven by challenge, I continuously explore new technologies, tools, and architectures to deepen my understanding and expand my impact. Core Skills: • Linux kernel & driver development • Embedded systems & board bring-up • System debugging & performance optimization • Git, Gerrit, Openwrt • C, C++, shell scripting

Experience

11 yrs 9 mos

Total Experience

5 yrs 7 mos

Average Tenure

6 mos

Current Experience

Qualcomm

Staff Engineer

Nov 2016 – Oct 2025 · 8 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Lead end-to-end design and implementation of Linux kernel device drivers and corresponding user space system components for Qualcomm Atheros WLAN chipsets used in access points, enabling full-stack WLAN functionality including initialization, configuration, diagnostics, and runtime management.
Designed and implemented user-kernel communication mechanisms including netlink, ioctl, and relayfs,
enabling efficient data exchange between kernel WLAN drivers and user space tools for runtime control,
high-volume diagnostics.
Managed a team of 4 engineers, handling feature design, code reviews, and release planning.
Designed and developed multiple generations of IEEE 802.11 protocols including 802.11be multi-link
operation and dynamic link reconfiguration.
Architected and implemented management frame reordering logic to ensure correct delivery sequencing in the Wi-Fi Host driver.
Led end-to-end development of Spectral Analysis for WLAN AP chipsets enabling interference detection and performance optimization.
Designed dynamic channel selection and channel management algorithms to reduce congestion and
improve communication efficiency.
Collaborated with upstream communities and internal stakeholders to ensure maintainable and scalable driver architecture.

ElectronicsEmbedded LinuxLinux kernel & driver developmentEmbedded systems & board bring-up

Broadcom limited

R&D Engineer Firmware I

Jun 2014 – Oct 2016 · 2 yrs 4 mos · Bengaluru Area, India · On-site

Developed firmware for 802.11 lower MAC controller in low-level assembly.
Developed low-level firmware for WLAN MAC on ARM Cortex-M cores using assembly and C.
Contributed to the development of market-leading low-power WLAN chipsets.
Involved in designing, prototyping and implementing a new ‘deep sleep state’ for ultra-low power
operation.
Implemented deep sleep modes and P2P power-saving techniques (NOA, CT window).
Developed patch infrastructure and ROMing framework for firmware updates.

ElectronicsFreeRTOSEmbedded systems & board bring-upFirmware development

Texas instruments

Summer Intern

May 2013 – Jul 2013 · 2 mos · Bangalore

Worked on low-power pattern generation and power-optimized transition fault testing (TFT).
Developed techniques to reduce power dissipation during at-speed testing using Cadence Encounter.