Jeenang Shah

Software Engineer

Hyderabad, Telangana, India3 yrs 11 mos experience

Most Likely To Switch

Key Highlights

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and Digital IC design.

Digital Ic DesignRtl CodingSystemverilogassertion(sva)

Problem SolvingMicroarchitectureVerilogSimulation and DebugSpyglassScriptingNAND FlashDesign Documents

3 yrs 11 mos

Total Experience

1 yr 11 mos

Average Tenure

2 yrs

Current Experience

2 roles

Promoted

May 2026 – Present · 1 mo · Hyderabad, Telangana, India

Problem SolvingDigital IC DesignMicroarchitectureRTL CodingVerilogSimulation and Debug+5

May 2024 – Apr 2026 · 1 yr 11 mos · Hyderabad, Telangana, India

ScriptingSpyglassDigital IC Design

2 roles

Dec 2023 – May 2024 · 5 mos · Hyderabad, Telangana, India

ScriptingSystemVerilogAssertion(SVA)

Jun 2022 – Dec 2023 · 1 yr 6 mos · Hyderabad, Telangana, India

ScriptingSystemVerilogAssertion(SVA)

Jan 2022 – Jun 2022 · 5 mos · Hyderabad, Telangana, India

Member of Compiler Tool Chain Development Team. Working on analysis tools development.
Developed APIs for extracting various data from reports generated by compiler.
Upgraded the regression framework by adding new feature testing.
Developed new testcases to check different functionality of tool.

ScriptingVerilogDigital IC Design

May 2021 – Jun 2021 · 1 mo

Member of ASIC Intern Team. Worked on the OpenROAD Project, for the execution of ASIC Flow.
Explored ASIC Design Flow from RTL file to the generation of GDS(Layout) File.
Learn about OpenROAD Project - an Open Source tool for IC design.
Executed PnR flow of the same on Linux Machine for sample design.
Documented the whole set-up and execution process along with the troubleshooting part.

VerilogDigital IC Design