Jyothi C O

Software Engineer

Bengaluru, Karnataka, India6 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Hardware-Firmware Co-Verification for SoC projects.
Proficient in UVM and System Verilog for functional verification.
Strong problem-solving skills demonstrated in high-stakes projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Hardware-Firmware Co-Verification.

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Skills

Core Skills

Hardware-firmware Co-verificationSystem-on-chip (soc) ProjectsFunctional Verification

Other Skills

Universal Verification Methodology (UVM)Synopsys toolsC++UVMSystem VerilogWork ethicInterpersonal SkillsGitHub CopilotMicrosoft Visual Studio CodeRust (Programming Language)Hardware Abstraction Layer (HAL)Shell ScriptingFormal VerificationDirect programming interface programmingAttention to Detail

About

I am a skilled enthusiastic DV Engineer with experience in silicon design and verification at leading semiconductor companies since 2019 September. I excel in programming languages, verification tools, problem-solving, projects execution and teamwork. ->Experienced in functional verification with expertise at IP level and Subsystem level verification. -> Proficient in Universal Verification Methodology (UVM), System Verilog (SV), Object Oriented Programming (OOP), C++, Verilog, C, Perl scripting, AMBA protocols, DJ-Make flow -> Expertise in HW Firmware co-verification of client/server/semi-custom/GPU/chiplet security architecture-based subsystems and System-on-Chip (SoC) projects, gaining valuable insights into diverse verification challenges. -> Passionate about continual knowledge expansion, staying updated with the latest advancements in the field and contributing to innovative semiconductor projects.

Experience

6 yrs 9 mos

Total Experience

3 yrs 4 mos

Average Tenure

4 yrs 2 mos

Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Promoted

Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · Hybrid

Security IP subsystem Hardware-Firmware Co-Verification: ARCH version 3.0
Worked on 20+ various high-stakes projects that involved technology changes, architectural model differences.
Sanitized the Microprocessor IP hardware interaction in the Security IP System which goes as a Subsystem to the System-On-Chip ICs
Implemented HW tests for SRAM and ROM memories preloading, Crypto engine verification, other sub-IPs at the subsystem level
Created and validated tests for local MPx transactions, inter-MPx communication and security gasket verification of the MP tiles at the Subsystem level.
Designed sanity tests for positive and negative scenarios using C++ ensuring robust functionality.
Developed and debugged tests for security gasket checking between the MP tiles.
Infrastructures development at subsystem level to accommodate various MPx and enable them for Inter-MP access through APIs using DJ & Make flow

Universal Verification Methodology (UVM)Synopsys toolsHardware-Firmware Co-VerificationSystem-on-Chip (SoC) Projects

Silicon Design Engineer 2

Apr 2022 – Jun 2024 · 2 yrs 2 mos · Bengaluru, Karnataka, India · Hybrid

Hardware-Firmware Co-Verification of System Management Unit IP / MegaIP : ARCH version 2.0
Secure boot and non-secure boot tests verification
Secure boot features verification in Client/Server/GPU/SCBU projects.
Verified for booting sequences which involve Cold boot, Warm boot, and secure boot flows.
Verified the critical features like S0I3 power state, cold reset and warm reset scenarios.
Conducted firmware images verification for various keys authentication and image recovery scenarios from alternate boot media during secure boot flow.
Developed and debugged negative tests for Firmware images verification.
Optimized the legacy tests for various features and improving functional coverage.
Security IP subsystem level H/W verification: ARCH version 2.0 to 3.0 migration
Developed the hardware sanity tests for multiple projects spec features verification
Automated the sanity tests generation through perl scripting
Regression management
Debugged and rootcaused various issues across the SMU/Subsystem projects

System VerilogUniversal Verification Methodology (UVM)Hardware-Firmware Co-VerificationFunctional Verification

Wafer space - an acl digital company

2 roles

Design Engineer 1

Sep 2019 – Apr 2022 · 2 yrs 7 mos · Bengaluru, Karnataka, India

DV training projects
Local projects include - 16 ports Router, Packet processing to Control and Data memories, AXI, AHB, I2C UVCs development
2 months training on physical design flow: conceptual understanding of each step with manual assignments solving.
Client Project: Texas Instruments
Worked on Computer Vision based RAW Front End IP verification

Work ethicInterpersonal Skills