J

JYOTSNA BHARDWAJ

Software Engineer

Rae Bareli, Uttar Pradesh, India4 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in Physical Design and Custom Compiler development.
  • Strong leadership and management skills in engineering projects.
  • Proficient in multiple Cadence tools for circuit design.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Circuit Engineering.

Contact

LinkedIn

Skills

Core Skills

Physical DesignManagementIo Design

Other Skills

Custom CompilerCadence Virtuoso Layout EditorCadence InnovusMicrosoft ExcelMicrosoft PowerPointMicrosoft WordLeadershipCadence GenusNI MultisimBBSIM

Experience

4 yrs 4 mos
Total Experience
2 yrs 2 mos
Average Tenure
3 yrs 1 mo
Current Experience

Ntpc limited

Executive Engineer

May 2023 – Present · 3 yrs 1 mo

Custom CompilerCadence Virtuoso Layout EditorCadence InnovusPhysical DesignMicrosoft ExcelMicrosoft PowerPoint+7

Synopsys inc

A&MS Circuit Design Engineer I

Feb 2022 – May 2023 · 1 yr 3 mos

IO DesignBBSIM

Education

Indian Institute of Technology, Delhi

Master of Technology - MTech — Integrated Electronics & Circuits

Jan 2019 – Jan 2021

Indian Institute of Technology (Indian School of Mines), Dhanbad

Bachelor of Technology - BTech — Electronics & Communication Engineering

Jan 2014 – Jan 2018

Jawahar Navodaya Vidyalaya - JNV

XII — PCM

Jan 2012 – Jan 2013

Jawahar Navodaya Vidyalaya, Raigarh, Chhattisgarh

X

Jan 2010 – Jan 2011

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