Karthik K Umesh — Software Engineer

Hi I am Karthik, I am a trained, skilled and experienced physical design verification engineer with a demonstrated history of working in latest technology nodes like 14nm, 10nm, 7nm. My top skills include: PnR, STA, PV with automation skills in tcl & perl. Following is a bird's eye view in to my career: Worked as Block owner for 2 years at Intel and the responsibilities included: - Owns block for PNR implementation and takes the design through all the stages upto closure. - Intercepts functional changes, Timing closure (Setup/Hold), Design Rule Violations, Reliability fixes etc.,(if any) which includes Cell insertion, Cell sizing, P/G Improvement etc. in ICC/ICC2. - Uses approved runsets in IC Validator based Physical verification/DFM flows. Project description Block level implementation of a sub system. Technology - 40nm, Macro count - 34, Standard cell count-38887, Area - 4.2 mm2, Supply - 1.1V, Power Budget - 600mW, IR drop < 55mV, clocks-5, metal layers -7 Tools: Synopsys IC Compiler & Synopsys Prime Time. Challenges: • Floor Planning: Positioning hard macros manually at the periphery using data flow diagram to optimize core utilization and meet area budget. • Power Planning: Reducing IR Drop to minimize Signal Integrity issues and to meet power budget with change in power distribution. • Timing Report analysis : Analysis of timing reports for false paths, multi cycle paths, logical DRCs, I/O constraints causing setup violations. • Placement and routing congestion analysis: Set up fixing with timing driven placement, congestion issues with change in floor plan and cell density. If you find my profile fits in to your requirement, reach out to me, I am looking out for exciting opportunities.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design Verification and Power Analysis.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 6 mos