Shreenidhi Rama Krishna — Product Engineer
GPU Silicon Physical Design Engineer with 6 years of experience. I am responsible for Netlist to GDSII implementation of GPU partitions. Have taped out multiple Multi power domain, switched partitions with 2M+ instances. Analysis and signoff of different aspects of PD such as Physical Design Verification, IR/IVD, Electromigration, STA, VCLP, LEQ Tools: Cadence Innovus / Cerebrus, Mentor Graphics Calibre, PrimeTime, Conformal Graduated with MS ECE from the University of Minnesota, Twin Cities. Passionate about every aspect of chip design from Architecture to Fabrication. Have special interest in Semiconductor devices, sensors and Domain Specific Computer Architecture. Experienced in Custom Circuit Design, Memories, Physical Design (RTL to GDSII) and Static Timing Analysis.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in GPU and Physical Design.
Location: San Diego, California, United States
Experience: 10 yrs 7 mos
Skills
- Physical Design
- Static Timing Analysis
- Process Control Engineering
- Safety Systems Design
- Control Logic Development
Career Highlights
- Expert in GPU Physical Design with extensive experience.
- Proficient in Static Timing Analysis and Physical Design Verification.
- Strong background in Semiconductor devices and Domain Specific Architectures.
Work Experience
Qualcomm
GPU Silicon PD Engineer, Staff (5 mos)
Apple
GPU Physical Design Engineer (5 yrs 4 mos)
Intel Corporation
CPU Core Physical Design Intern (6 mos)
Yokogawa
Process Control Engineer (3 yrs 11 mos)
Schneider Electric
Research Intern (11 mos)
Education
MS in Electrical & Computer Engineering at University of Minnesota
Bachelor of Engineering (BE) at Sri Jayachamarajendra College Of Engineering
Pre-University at Vidyodaya Pre University College, Udupi
