Karthikeyan B

CTO

Bengaluru, Karnataka, India14 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

14+ years in semiconductor industry.
Expert in SOC verification and validation.
Proven leadership in high-performance teams.

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in functional safety and validation.

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Skills

Core Skills

Verification And Validation (v&v)Failure Analysis

Other Skills

SpecmanNCSimVerilogVHDLModelSimAltera QuartusVLSIRTL designCFPGAFunctional VerificationC++RTL codingASICXilinx

About

An enthusiastic engineer with 14+ years of professional experience in various aspects of the semiconductor Industry :(PreSi/PostSi validation, emulation & functional safety architecture analysis) Goals: To Learn/Work/Innovate on cutting-edge technologies in the semiconductor domain, to create a positive impact on people's lives every day Specialties: 1)Quick learning of new tools/languages. 2)Ability to communicate with cross-teams wherever required. 3)Ability to lead high-performance teams. 4)Ability to work individually/team. 5)Believe in value-based relationships.

Experience

14 yrs 1 mo

Total Experience

2 yrs 9 mos

Average Tenure

5 yrs 8 mos

Current Experience

Intel corporation

3 roles

Technical Leader

Jun 2025 – Present · 1 yr · Hybrid

SoC Functional Validation Engineer

Promoted

Oct 2020 – Present · 5 yrs 8 mos · Hybrid

Leading Validation activities for Next-gen Intel Server Products

Verification and Validation (V&V)

Functional Safety Engineer

Mar 2016 – Nov 2018 · 2 yrs 8 mos · Bangalore

Worked on Functional Safety Architecture Analysis of Flagship SOCs designed by Intel :
Responsible for Architecture analysis of the SoCs that are targetted for Automotive and Industrial markets to comply with Safety Standards (ISO26262, IEC61508) which includes, performing, Failure Mode Effective Analysis, Dependent Failure Analysis, Requirements Generation & Certification from the External body.
 Responsible for performing Architecture analysis for a SoC targeted for Automotive market
Ownership for Failure Mode Analysis (FMEDAs) of the set of IPs in the SoC
Responsible for generating HW/SW requirements based on the outcomes of Safety Analysis
Responsible for performing Dependent Failure Analysis(DFA) at SoC level
Responsible for generation of Safety Verification Plan & supporting the Fault Injection for the same
Collaborated with cross-site teams to understand the requirements & for Reviews.

Failure Analysis

Qualcomm

Lead Engineer, Sr

Nov 2018 – Oct 2020 · 1 yr 11 mos · Banaglore

Worked on ARM-based Mobile SOCs designed by Qualcomm :
Complete ownership of verifying the Boot Flows at SOC level for different SKUs (Mobile/Modem) with all supported boot Interfaces.
Complete ownership of verifying the Quality Manager IP at SOC level.
Involved in pre-silicon verification of concurrency/coherency aspects at SOC level.

Verification and Validation (V&V)

Freescale semiconductor

Senior Design Engineer

Jan 2013 – Feb 2016 · 3 yrs 1 mo · Bangalore

Worked on ARM-based Digital Networking devices with LayerScape Architecture (28nm node):
Complete ownership of verifying the Boot flow with BIOS Image with all supported boot interfaces.
Complete ownership of verifying the following interfaces (GPIO, I2C)
Involved in verification activities for Reset/Clock related blocks
Involved in the verification of Low power verification with secure boot entry and exit
Involved in Post- silicon validation of Boot flow & WDOG timer module.

Verification and Validation (V&V)